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| this is information on a product in full production. november 2012 doc id 023683 rev 1 1/97 1 stm32f050x4 stm32f050x6 low- and medium-density advanc ed arm?-based 32-bit mcu with up to 32 kbytes flash, timers, adc and comm. interfaces datasheet ? production data features core: arm 32-bit cortex?-m0 cpu, frequency up to 48 mhz memories ? 16 to 32 kbytes of flash memory ? 4 kbytes of sram with hw parity checking crc calculation unit reset and supply management ? voltage range: 2.0 v to 3.6 v ? power-on/power-down reset (por/pdr) ? programmable voltage detector (pvd) ? low power modes: sleep, stop and standby ?v bat supply for rtc and backup registers clock management ? 4 to 32 mhz crystal oscillator ? 32 khz oscillator for rtc with calibration ? internal 8 mhz rc with x6 pll option ? internal 40 khz rc oscillator up to 39 fast i/os ? all mappable on external interrupt vectors ? up to 25 i/os with 5 v tolerant capability 5-channel dma controller 1 12-bit, 1.0 s adc (up to 10 channels) ? conversion range: 0 to 3.6v ? separate analog supply from 2.4 up to 3.6 v up to 9 timers ? 1 x 16-bit 7-channel advanced-control timer for 6 channels pwm output, with deadtime generation and emergency stop ? 1 x 32-bit and 1 x 16-bit timer, with up to 4 ic/oc, usable for ir control decoding ? 1 x 16-bit timer, with 2 ic/oc, 1 ocn, deadtime generation and emergency stop ? 1 x 16-bit timer, with ic/oc and ocn, deadtime generation, emergency stop and modulator gate for ir control ? 1 x 16-bit timer with 1 ic/oc ? independent and system watchdog timers ? systick timer: 24-bit downcounter calendar rtc with alarm and periodic wakeup from stop/standby communication interfaces ? 1 x i 2 c interface; supporting fast mode plus (1 mbit/s) with 20 ma current sink, smbus/pmbus, and wakeup from stop ? 1 x usart supporting master synchronous spi and modem control; one with iso7816 interface, lin, irda capability auto baud rate detection and wakeup feature ? 1 x spi (18 mbit/s) with 4 to 16 programmable bit frames, with i 2 s interface multiplexed serial wire debug (swd) 96-bit unique id extended temperature range: -40 to +105c table 1. device summary reference part number stm32f050x4 stm32f050f4, stm32f050g4, stm32f050k4, stm32f050c4 stm32f050x6 stm32f050f6, stm32f050g6, stm32f050k6, stm32f050c6 lqfp48 7x7 ufqfpn32 5x5 tssop20 ufqfpn28 4x4 www.st.com
contents stm32f050xx 2/97 doc id 023683 rev 1 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 arm? cortextm-m0 core with embedded flash and sram . . . . . . . . . 12 3.2 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 cyclic redundancy check calculation unit (crc) . . . . . . . . . . . . . . . . . . . 13 3.5 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.2 power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7 general-purpose inputs/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 direct memory access controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.9 interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.9.1 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 16 3.9.2 extended interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . . 16 3.10 analog to digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10.1 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10.2 internal voltage reference (v refint ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.11 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11.1 advanced-control timer (tim1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11.2 general-purpose timers (tim2..3, tim14..17) . . . . . . . . . . . . . . . . . . . . 18 3.11.3 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.11.4 system window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.11.5 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12 real-time clock (rtc) and backup registers . . . . . . . . . . . . . . . . . . . . . . 20 3.13 inter-integrated circuit interface (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14 universal synchronous/asynchronous receiver transmitter (usart) . . . 21 3.15 serial peripheral interface (spi)/inter-integrated sound interfaces (i 2 s) . 22 stm32f050xx contents doc id 023683 rev 1 3/97 3.16 serial wire debug port (sw-dp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.3.2 operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 40 6.3.3 embedded reset and power control block characteristics . . . . . . . . . . . 40 6.3.4 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.3.6 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.3.7 internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.8 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.9 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.3.10 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.3.11 electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.12 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.13 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3.14 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.3.15 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3.16 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.17 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.18 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.19 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 contents stm32f050xx 4/97 doc id 023683 rev 1 7 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.2.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 93 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 stm32f050xx list of tables doc id 023683 rev 1 5/97 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f050xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6. comparison of i2c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 8. pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 9. alternate functions selected through gpioa_afr registers for port a . . . . . . . . . . . . . . . 30 table 10. alternate functions selected through gpiob_afr registers for port b . . . . . . . . . . . . . . . 31 table 11. stm32f050x peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 12. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 13. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 14. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 15. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 16. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 17. embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 18. programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 19. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 table 20. typical and maximum current consumption from v dd supply at vdd = 3.6 . . . . . . . . . . . 43 table 21. typical and maximum current consumption from the v dda supply . . . . . . . . . . . . . . . . . . 44 table 22. typical and maximum v dd consumption in stop and standby modes. . . . . . . . . . . . . . . . 45 table 23. typical and maximum v dda consumption in stop and standby modes. . . . . . . . . . . . . . . 45 table 24. typical and maximum current consumption from v bat supply. . . . . . . . . . . . . . . . . . . . . . 46 table 25. typical current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 26. typical current consumption in sleep mode, code running from flash or ram . . . . . . . . . 48 table 27. switching output i/o current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 28. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 29. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 30. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 31. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 32. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 33. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 34. hsi14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 35. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 36. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 37. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 38. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 39. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 40. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 41. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 42. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 43. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 44. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 45. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 46. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 47. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 list of tables stm32f050xx 6/97 doc id 023683 rev 1 table 48. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 49. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 50. r ain max for f adc = 14 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 51. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 52. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 53. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 54. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 55. iwdg min/max timeout period at 40 khz (lsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 56. wwdg min-max timeout value @48 mhz (pclk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 57. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 58. i2c analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 59. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 60. i 2 s characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 61. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 85 table 62. ufqfpn32 ? 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 63. ufqfpn28 ? 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 64. tssop20 ? 20-pin thin shrink small outline package mechanical data . . . . . . . . . . . . . . . 91 table 65. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 66. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 stm32f050xx list of figures doc id 023683 rev 1 7/97 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 3. lqfp48 48-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 4. ufqfpn32 32-pin package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 5. ufqfpn28 28-pin package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 6. tssop20 20-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 figure 7. stm32f050xx memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 figure 8. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 9. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 10. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 11. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 12. high-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 13. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 14. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 15. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 16. hsi oscillator accuracy characte rization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 17. hsi14 oscillator accuracy charac terization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 18. tc and tta i/o input characteristics - cmos port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 19. tc and tta i/o input characteristics - ttl port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 20. five volt tolerant (ft and ftf) i/o input characteristics - cmos port. . . . . . . . . . . . . . . . . 68 figure 21. five volt tolerant (ft and ftf) i/o input characteristics - ttl port . . . . . . . . . . . . . . . . . . . 68 figure 22. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 23. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 24. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 25. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 26. i 2 c bus ac waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 27. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 28. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 29. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 30. i2s slave timing diagram (philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 31. i2s master timing diagram (ph ilips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 32. lqfp48 - 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 85 figure 33. lqfp48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 34. ufqfpn32 - 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package outline . . . 87 figure 35. ufqfpn32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 36. ufqfpn28 - 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package outline . . . 89 figure 37. ufqfpn28 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 38. tssop20 - 20-pin thin shrink small outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 39. tssop20 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 introduction stm32f050xx 8/97 doc id 023683 rev 1 1 introduction this datasheet provides the ordering information and mechanical device characteristics of the stm32f050x4 and stm32f050x6 microcontrollers, hereafter referred to as stm32f050xx. this datasheet should be read in conjunction with the stm32f0xxxx reference manual (rm0091). the reference manual is available from the stmicroelectronics website www.st.com. for information on the arm cortex?-m0 core, please refer to the cortex?-m0 technical reference manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0432c/index.html. stm32f050xx description doc id 023683 rev 1 9/97 2 description the stm32f050xx family incorporates the high-performance arm cortex?-m0 32-bit risc core operating at a 48 mhz maximum frequency, high-speed embedded memories (flash memory up to 32 kbytes and sram up to 4 kbytes), and an extensive range of enhanced peripherals and i/os. all devices offer standard communication interfaces (one i 2 c, one spi, one i2s, and one usart), one 12-bit adc, up to five general-purpose 16-bit timers, a 32-bit timer and an advanced-control pwm timer. the stm32f050xx family operates in the -40 to +85 c and -40 to +105 c temperature ranges, from a 2.0 to 3.6 v power supply. a comprehensive set of power-saving modes allows the design of low-power applications. the stm32f050xx family includes devices in five different packages ranging from 20 pins to 48 pins. depending on the device chosen, different sets of peripherals are included. an overview of the complete range of peripherals proposed in this family is provided. these features make the stm32f050xx microcontroller family suitable for a wide range of applications such as control application and user interfaces, handheld equipment, a/v receivers and digital tv, pc peripherals, gaming and gps platforms, industrial applications, plcs, inverters, printers, scanners, alarm systems, video intercoms, and hvacs. description stm32f050xx 10/97 doc id 023683 rev 1 table 2. stm32f050xx family device features and peripheral counts peripheral stm32f050fx stm32f 050gx stm32f050kx stm32f050cx flash (kbytes) 16 32 16 32 16 32 16 32 sram (kbytes) 4 4 4 4 timers advanced control 1 (16-bit) general purpose 4 (16-bit) 1 (32-bit) comm. interfaces spi (i2s) (1) 1 i 2 c1 usart 1 12-bit synchronized adc (number of channels) 1 (9 ext. + 3 int.) 1 (10 ext. + 3 int.) gpios 15232739 max. cpu frequency 48 mhz operating voltage 2.0 to 3.6 v operating temperature ambient operating temperature: -40 c to 85 c / -40 c to 105 c junction temperature: -40c to 105c / -40 c to 125 c packages tssop20 ufqfpn28 ufqfpn32 lqfp48 1. the spi interface can be used either in spi mode or in i2s audio mode. stm32f050xx description doc id 023683 rev 1 11/97 figure 1. block diagram 0 ! ; = % 8 4 ) 4 . 6 ) # 3 7 # , + 3 7 $ ! 4 . 2 3 4 6 $ $ t o 6 ! & ! ( " 3 2 ! - 7 + 5 0 6 3 3 ' 0 $ - ! c h a n n e l s 8 4 ! , / 3 # - ( z 8 4 ! , k ( z / 3 # ) . 0 & / 3 # / 5 4 0 & / 3 # ? / 5 4 / 3 # ? ) . ! ( " 0 # , + ( # , + ! 0 " 0 # , + & , ! 3 ( 6 / , 4 2 % ' 6 4 / 6 6 $ $ 0 / 7 % 2 2 4 # i n t e r f a c e a s ! & " u s - a t r i x b i t s ) n t e r f a c e + " 2 4 # # / 2 4 % 8 - # 0 5 f ( # , + - ( z o b l f l a s h " a c k u p r e g 3 # , 3 $ ! 3 - " a l ) # a s ! & c h a n n e l s c o m p l c h a n n e l s " 2 + % 4 2 i n p u t a s ! & c h % 4 2 a s ! & & # , + 0 o w e r ) 7 $ ' 6 $ $ 6 3 7 0 / 2 0 $ 2 3 5 0 0 , 9 6 $ $ ! 6 $ $ ! 6 " ! 4 6 t o 6 2 8 4 8 # 4 3 2 4 3 # + a s ! & . 6 ) # 3 0 ) ) 3 # o n t r o l l e r 6 $ $ ! 3 5 0 % 2 6 ) 3 ) / . 0 6 $ 2 e s e t ) n t 6 $ $ ! 0 " 0 / 2 4 ! - 0 % 2 2 4 # 2 % 3 % 4 # , / # + # / . 4 2 / , ! $ # # , + 0 , , ! , ! 2 - / 5 4 3 e r i a l 7 i r e $ e b u g # % # # , + - ) 3 / - # + 0 " ; = 0 # ; = 0 & ; = c h % 4 2 a s ! & c h a n n e l a s ! & 6 $ $ + " 2 # ( 3 - ( z 5 3 ! 2 4 # , + c h a n n e l c o m p l " 2 + a s ! & c h a n n e l c o m p l " 2 + a s ! & c o n t r o l l e r 3 2 ! - 3 9 3 # & ' ) & m ! f o r & - ) 2 ? / 5 4 a s ! & $ " ' - # 5 ! ( " d e c o d e r - 3 6 4 ) - % 2 4 ) - % 2 4 ) - % 2 4 ) - % 2 4 ) - % 2 4 ) - % 2 5 3 ! 2 4 ' 0 ) / p o r t ! ' 0 ) / p o r t " ' 0 ) / p o r t # ' 0 ) / p o r t & b i t ! $ # ! $ # ? ) . 6 $ $ ! 4 e m p s e n s o r 6 3 3 ! 6 $ $ ! ) & 2 # ( 3 - ( z 2 # , 3 3 # + # + - / 3 ) 3 $ . 3 3 7 3 a s ! & 7 7 $ ' # 2 # functional overview stm32f050xx 12/97 doc id 023683 rev 1 3 functional overview 3.1 arm ? cortex tm -m0 core with embedded flash and sram the arm cortex?-m0 processor is the latest generation of arm processors for embedded systems. it has been developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. the arm cortex?-m0 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the stm32f050xx family has an embedded arm core and is therefore compatible with all arm tools and software. figure 1 shows the general block diagram of the device family. 3.2 memories the device has the following features: 4 kbytes of embedded sram accessed (read /write) at cpu clock speed with 0 wait states and featuring embedded parity checking with exception generation for fail-critical applications. the non-volatile memory is divided into two arrays: ? 16 to 32 kbytes of embedded flash memory for programs and data ?option bytes the option bytes are used to write-protect the memory (with 4 kb granularity) and/or readout-protect the whole memory with the following options: ? level 0: no readout protection ? level 1: memory readout protection, the flash memory cannot be read from or written to if either debug features are connected or boot in ram is selected ? level 2: chip readout protection, debug features (cortex-m0 serial wire) and boot in ram selection disabled 3.3 boot modes at startup, the boot pin and boot selector option bit are used to select one of three boot options: boot from user flash boot from system memory boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1. stm32f050xx functional overview doc id 023683 rev 1 13/97 3.4 cyclic redundancy check calculation unit (crc) the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a crc-32 (ethernet) polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc ca lculation unit helps co mpute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. 3.5 power management 3.5.1 power supply schemes v dd = 2.0 to 3.6 v: external power supply for i/os and the internal regulator. provided externally through v dd pins. v dda = 2.0 to 3.6 v: external analog power supply for adc, reset blocks, rcs and pll (minimum voltage to be applied to v dda is 2.4 v when the adc is used). the v dda voltage level must be always greater or equal to the v dd voltage level and must be provided first. v bat = 1.65 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. 3.5.2 power supply supervisors the device has integrated power-on reset (por) and power-down reset (pdr) circuits. they are always active, and ensure proper operation above a threshold of 2 v. the device remains in reset mode when the monitored supply voltage is below a specified threshold, v por/pdr , without the need for an external reset circuit. the por monitors only the v dd supply voltage. during the startup phase it is required that v dda should arrive first and be greater than or equal to v dd . the pdr monitors both the v dd and v dda supply voltages, however the v dda power supply supervisor can be disabled (by programming a dedicated option bit) to reduce the power consumption if the application design ensures that v dda is higher than or equal to v dd . the device features an embedded programmable voltage detector (pvd) that monitors the v dd power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd drops below the v pvd threshold and/or when v dd is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. functional overview stm32f050xx 14/97 doc id 023683 rev 1 3.5.3 voltage regulator the regulator has three operating modes: main (mr), low power (lpr) and power down. mr is used in normal operating mode (run) lpr can be used in stop mode where the power demand is reduced power down is used in standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing ze ro consumption (but the contents of the registers and sram are lost) this regulator is always enabled after reset. it is disabled in standby mode, providing high impedance output. 3.5.4 low-power modes the stm32f050xx family supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. stop mode stop mode achieves very low power consumption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are di sabled. the voltage regulator can also be put either in normal or in low power mode. the device can be woken up from stop mode by any of the exti lines. the exti line source can be one of the 16 external lines, the pvd output, rtc alarm, i2c1 or usart1. the i2c1 and the usart1 can be configur ed to enable the hsi rc oscillator for processing incoming data. if this is used, the voltage regulator should not be put in the low-power mode but kept in normal mode. standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.8 v domain is powered off. the pll, the hsi rc and the hse crystal oscillators are also switched off. after entering standby mode, sram and register contents are lost except for registers in the backup domain and standby circuitry. the device exits standby mode when an external reset (nrst pin), a iwdg reset, a rising edge on the wkup pins, or an rtc alarm occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped by entering stop or standby mode. stm32f050xx functional overview doc id 023683 rev 1 15/97 3.6 clocks and startup system clock selection is performed on startup, however the internal rc 8 mhz oscillator is selected as default cpu clock on reset. an ex ternal 4-32 mhz clock can be selected, in which case it is monitored for failure. if failure is detected, the system automatically switches back to the internal rc oscillato r. a software interrupt is genera ted if enabled. similarly, full interrupt management of the pll clock entry is available when necessary (for example on failure of an indirectly used extern al crystal, resonator or oscillator). several prescalers allow the application to configure the frequency of the ahb and the apb domains. the maximum frequency of t he ahb and the apb domains is 48 mhz. figure 2. clock tree - ( z ( 3 % / 3 # / 3 # ? ) . / 3 # ? / 5 4 / 3 # ? ) . / 3 # ? / 5 4 - ( z ( 3 ) 2 # t o ) 7 $ ' 0 , , x x x 0 , , - 5 , - # / - a i n c l o c k o u t p u t ! ( " 0 , , # , + ( 3 ) ( 3 % ! 0 " p r e s c a l e r ! $ # 0 r e s c a l e r ( # , + 0 , , # , + t o ! ( " b u s c o r e m e m o r y a n d $ - ! t o ! $ # - ( z m a x , 3 % , 3 ) ( 3 ) ( 3 ) ( 3 % t o 2 4 # 0 , , 3 2 # 3 7 - # / 3 9 3 # , + 2 4 # # , + 2 4 # 3 % , ; = ) 7 $ ' # , + 3 9 3 # , + t o 4 ) - ) f ! 0 " p r e s c a l e r x e l s e x & , ) 4 & # , + t o & l a s h p r o g r a m m i n g i n t e r f a c e ( 3 ) - ( z ( 3 ) 2 # ( 3 ) t o ) # t o 5 3 ! 2 4 , 3 % ( 3 ) 3 9 3 # , + 0 # , + 3 9 3 # , + ( 3 ) 0 # , + - 3 6 t o ) 3 t o c o r t e x 3 y s t e m t i m e r & ( # , + # o r t e x f r e e r u n n i n g c l o c k t o ! 0 " p e r i p h e r a l s ! ( " p r e s c a l e r # 3 3 , 3 % / 3 # k ( z , 3 ) 2 # k ( z , 3 ) , 3 % functional overview stm32f050xx 16/97 doc id 023683 rev 1 3.7 general-purpose in puts/outputs (gpios) each of the gpio pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. the i/o configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. 3.8 direct memory access controller (dma) the 5-channel general-purpose dmas manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. the dma supports circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. each channel is connected to dedicated hardware dma requests, with support for software trigger on each channel. configuration is made by software and transfer sizes between source and destination are independent. dma can be used with the main peripherals: spi, i2s, i2c, usart, all timx timers (except tim14) and adc. 3.9 interrupts and events 3.9.1 nested vectored interrupt controller (nvic) the stm32f050xx family embeds a nested vectored interrupt controller able to handle up to 32 maskable interrupt channels (not including the 16 interrupt lines of cortex?-m0) and 4 priority levels. closely coupled nvic gives low latency interrupt processing interrupt entry vector table address passed directly to the core closely coupled nvic core interface allows early processing of interrupts processing of late arriving higher priority interrupts support for tail-chaining processor state automatically saved interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimal interrupt latency. 3.9.2 extended interrupt /event controller (exti) the external interrupt/event controller consists of 24 edge detector lines used to generate interrupt/event requests and wake-up the system. each line can be independently configured to select the trigge r event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal clock period. up to 39 gpios can be connected to the 16 external interrupt lines. stm32f050xx functional overview doc id 023683 rev 1 17/97 3.10 analog to digital converter (adc) the 12-bit analog to digital converter has up to 16 external and 3 internal (temperature sensor, voltage reference, vbat voltage measurement) channels and performs conversions in single-shot or scan modes. in scan mode, automatic conversion is performed on a selected group of analog inputs. the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. 3.10.1 temperature sensor the temperature sensor (ts) generates a voltage v sense that varies linearly with temperature. the temperature sensor is internally connected to the adc_in16 input channel which is used to convert the sensor output voltage into a digital value. the sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. as the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. to improve the accuracy of the temperat ure sensor measurement, each device is individually factory-calibrated by st. the temperature sensor factory calibration data are stored by st in the system memory area, accessible in read-only mode. 3.10.2 internal voltage reference (v refint ) the internal voltage reference (v refint ) provides a stable (bandgap) voltage output for the adc. v refint is internally connected to the adc_in17 input channel. the precise voltage of v refint is individually measured for each part by st during production test and stored in the system memory area. it is accessible in read-only mode. table 3. temperature sensor calibration values calibration value name description memory address ts_cal1 ts adc raw data acquired at temperature of 30 c, v dda = 3.3 v 0x1fff f7b8 - 0x1fff f7b9 ts_cal2 ts adc raw data acquired at temperature of 110 c v dda = 3.3 v 0x1fff f7c2 - 0x1fff f7c3 table 4. temperature sensor calibration values calibration value name description memory address vrefint_cal raw data acquired at temperature of 30 c v dda = 3.3 v 0x1fff f7ba - 0x1fff f7bb functional overview stm32f050xx 18/97 doc id 023683 rev 1 3.11 timers and watchdogs the stm32f050xx family devices include up to six general-purpose timers, one basic timer and an advanced control timer. ta bl e 5 compares the features of the advanced-control, general-purpose and basic timers. 3.11.1 advanced-control timer (tim1) the advanced-control timer (tim1) can be seen as a three-phase pwm multiplexed on 6 channels. it has complementary pwm outputs with programmable inserted dead times. it can also be seen as a complete general-purpose timer. the 4 independent channels can be used for: input capture output compare pwm generation (edge or center-aligned modes) one-pulse mode output if configured as a standard 16-bit timer, it has the same features as the timx timer. if configured as the 16-bit pw m generator, it has full modu lation capability (0-100%). the counter can be frozen in debug mode. many features are shared with those of the standard timers which have the same architecture. the advanced control timer can therefore work together with the other timers via the timer link feature for synchronization or event chaining. 3.11.2 general-purpose timers (tim2..3, tim14..17) there are six synchronizable general-purpose timers embedded in the stm32f050xx devices (see ta bl e 5 for differences). each general-purpose timer can be used to generate pwm outputs, or as simple time base. table 5. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/compare channels complementary outputs advanced control tim1 16-bit up, down, up/down any integer between 1 and 65536 ye s 4 ye s general purpose tim2 32-bit up, down, up/down any integer between 1 and 65536 ye s 4 n o tim3 16-bit up, down, up/down any integer between 1 and 65536 ye s 4 n o tim14 16-bit up any integer between 1 and 65536 no 1 no tim16, tim17 16-bit up any integer between 1 and 65536 ye s 1 ye s stm32f050xx functional overview doc id 023683 rev 1 19/97 tim2, tim3 stm32f050xx devices feature two synchronizable 4-channel general-purpose timers. tim2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. tim3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. they feature 4 independent channels each for input capture/output compare, pwm or one-pulse mode output. this gives up to 12 input captures/output compares/pwms on the largest packages. the tim2 and tim3 general-purpose timers can work together or with the tim1 advanced- control timer via the timer link feature for synchronization or event chaining. tim2 and tim3 both have independent dma request generation. these timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. their counters can be frozen in debug mode. tim14 this timer is based on a 16-bit auto-re load upcounter and a 16-bit prescaler. tim14 features one single channel for input capture/output compare, pwm or one-pulse mode output. its counter can be frozen in debug mode. tim16 and tim17 these timers are based on a 16-bit auto-r eload upcounter and a 16-bit prescaler. tim16 and tim17 feature one single channel for input capture/output compare, pwm or one-pulse mode output. tim16, and tim17 have a complementary output with dead-time generation and independent dma request generation their counters can be frozen in debug mode. 3.11.3 independent watchdog (iwdg) the independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user- defined refresh window. it is clocked from an independent 40 khz internal rc and as it operates independently from the main clock, it can operate in stop and standby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. 3.11.4 system wind ow watchdog (wwdg) the system window watchdog is based on a 7-bit downcounter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the apb clock (pclk). it has an early warning interrupt capability and the counter can be frozen in debug mode. functional overview stm32f050xx 20/97 doc id 023683 rev 1 3.11.5 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard down counter. it features: a 24-bit down counter autoreload capability maskable system interrupt generation when the counter reaches 0. programmable clock source (hclk or hclk/8) 3.12 real-time clock (rtc) and backup registers the rtc and the 5 backup registers are supplied through a switch that takes power either on v dd supply when present or through the v bat pin. the backup registers are five 32-bit registers used to store 20 bytes of user application data when v dd power is not present. they are not reset by a system or power reset, or when the device wakes up from standby mode. the rtc is an independent bcd timer/counter. its main features are the following: calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in bcd (binary-coded decimal) format. automatically correction for 28, 29 (leap year), 30, and 31 day of the month. programmable alarm with wake up from stop and standby mode capability. on-the-fly correction from 1 to 32767 rtc clock pulses. this can be used to synchronize it with a master clock. digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy. 2 anti-tamper detection pins with programmable filter. the mcu can be woken up from stop and standby modes on tamper event detection. timestamp feature which can be used to save the calendar content. this function can triggered by an event on the timestamp pin, or by a tamper event. the mcu can be woken up from stop and standby modes on timestamp event detection. the rtc clock sources can be: a 32.768 khz external crystal a resonator or oscillator the internal low-power rc oscillator (typical frequency of 40 khz) the high-speed external clock divided by 32. stm32f050xx functional overview doc id 023683 rev 1 21/97 3.13 inter-integrated circuit interface (i 2 c) the i 2 c interface (i2c1) can operate in multimaster or slave mode. it can support standard mode (up to 100 kbit/s), fast mode (up to 400 kbit/s) and fast mode plus (up to 1 mbit/s) with 20 ma output drive. it supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). it also includes programmable analog and digital noise filters. in addition, i2c1 provides hardware support for smbus 2.0 and pmbus 1.1: arp capability, host notify protocol, hardware crc (pec) generation/verification, timeouts verifications and alert protocol management. i2c1 also has a clock domain independent from the cpu clock, allowing the i2c1 to wake up the mcu from stop mode on address match. the i2c interface can be served by the dma controller. 3.14 universal synchronous/asynchronous receiver transmitter (usart) the device embeds an universal synchronous/asynchronous receiver transmitters (usart1), which communicates at speeds of up to 6 mbit/s. it provides hardware management of the cts, rts and rs485 de signals, multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode. it also supports smartcard communication (iso 7816), irda sir endec, lin master/slave capability, auto baud rate feature and has a clock domain independent from the cpu clock, allowing it to wake up the mcu from stop mode. the usart interface can be served by the dma controller. table 6. comparison of i2c analog and digital filters analog filter digital filter pulse width of suppressed spikes 50 ns programmable length from 1 to 15 i2c peripheral clocks benefits available in stop mode 1. extra filtering capability vs. standard requirements. 2. stable length drawbacks variations depending on temperature, voltage, process wakeup from stop on address match is not available when digital filter is enabled. functional overview stm32f050xx 22/97 doc id 023683 rev 1 3.15 serial peripheral interface (spi)/inter-integrated sound interfaces (i 2 s) the spi (spi1) is able to communicate up to 18 mbits/s in slave and master modes in full- duplex and half-duplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. one standard i 2 s interface (multiplexed with spi1) supporting four different audio standards can operate as master or slave at half-duplex communication mode. it can be configured to transfer 16 and 24 or 32 bits with16-bit or 32-bit data resolution and synchronized by a specific signal. audio sampling frequency from 8 khz up to 192 khz can be set by 8-bit programmable linear prescaler. when operating in master mode it can output a clock for an external audio component at 256 times the sampling frequency. 3.16 serial wire debug port (sw-dp) an arm sw-dp interface is provided to allow a serial wire debugging tool to be connected to the mcu. stm32f050xx pinouts and pin description doc id 023683 rev 1 23/97 4 pinouts and pin description figure 3. lqfp48 48-pin package pinout figure 4. ufqfpn32 32-pin package pinout , 1 & 0 0 ! 0 ! 0 ! 0 ! 0 ! 0 " 0 " 0 " 0 " 0 " 6 3 3 6 $ $ 0 & 0 & 0 ! 0 ! 0 ! 0 ! 0 ! 0 ! 0 " 0 " 0 " 0 " 6 " ! 4 . 2 3 4 6 3 3 ! 6 $ $ ! 0 ! 0 ! 0 ! 6 $ $ 6 3 3 0 " 0 " " / / 4 0 " 0 " 0 " 0 " 0 " 0 ! 0 ! - 3 6 0 # 0 # / 3 # ? ) . 0 & / 3 # ? ) . 0 & / 3 # ? / 5 4 0 # / 3 # ? / 5 4 0 ! 6 $ $ . 2 3 4 0 ! 0 ! 0 ! 0 ! 0 ! 0 " 0 ! 6 $ $ 0 ! 0 ! 0 ! 0 ! 0 ! 0 ! 0 " " / / 4 0 " 0 " 0 " - 3 6 6 $ $ ! 0 " 0 " 0 ! 0 " 0 " 0 ! 0 & / 3 # ? ) . 0 & / 3 # ? / 5 4 0 ! 6 3 3 6 3 3 ! pinouts and pin description stm32f050xx 24/97 doc id 023683 rev 1 figure 5. ufqfpn28 28-pin package pinout figure 6. tssop20 20-pin package pinout 0 ! 0 ! 0 ! 0 " 0 ! 0 ! 0 ! 6 $ $ ! 0 & / 3 # ? ) . . 2 3 4 " / / 4 6 $ $ 6 3 3 0 " 0 ! 0 ! 0 ! 0 " 0 " 0 ! 0 ! 0 " 0 " 0 " 0 & / 3 # ? / 5 4 - 3 6 0 ! 0 ! 0 ! - 3 6 0 & / 3 # ? ) . " / / 4 0 & / 3 # ? / 5 4 . 2 3 4 6 $ $ ! 0 ! 0 ! 6 $ $ 0 ! 0 ! 0 ! 0 " 6 3 3 0 ! 0 ! 0 ! 0 ! 0 ! 0 ! 0 ! stm32f050xx pinouts and pin description doc id 023683 rev 1 25/97 table 7. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o ftf 5 v tolerant i/o, fm+ capable tta 3.3 v tolerant i/o directly connected to adc tc standard 3.3v i/o b dedicated boot0 pin rst bidirectional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset pin functions alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabled through peripheral registers pinouts and pin description stm32f050xx 26/97 doc id 023683 rev 1 table 8. pin definitions pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp48 ufqfpn32 ufqfpn28 tssop20 alternate functions additional functions 1 - - - vbat s backup power supply 2- - - pc13 i/otc (1)(2) rtc_tamp1, rtc_ts, rtc_out, wkup2 3- - - pc14/osc32_in (pc14) i/o tc (1)(2) osc32_in 4- - - pc15/osc32_out (pc15) i/o tc (1)(2) osc32_out 52 2 2 pf0/osc_in (pf0) i/o ft osc_in 63 3 3 pf1/osc_out (pf1) i/o ft osc_out 7 4 4 4 nrst i/o rst device reset input / internal reset output (active low) 8 0 - - vssa s analog ground 9 5 5 5 vdda s analog power supply 10 6 6 6 pa0 i/o tta tim2_ch1_etr, usart1_cts (3) adc_in0, rtc_tamp2, wkup1 11 7 7 7 pa1 i/o tta tim2_ch2, eventout, usart1_rts (3) adc_in1 12 8 8 8 pa2 i/o tta tim2_ch3, usart1_tx (3) adc_in2 13 9 9 9 pa3 i/o tta tim2_ch4, usart1_rx (3) adc_in3 14 10 10 10 pa4 i/o tta spi1_nss, i2s1_ws, tim14_ch1, usart1_ck (3) adc_in4 15 11 11 11 pa5 i/o tta spi1_sck, i2s1_ck, tim2_ch1_etr adc_in5 stm32f050xx pinouts and pin description doc id 023683 rev 1 27/97 16 12 12 12 pa6 i/o tta spi1_miso, i2s1_mck, tim3_ch1, tim1_bkin, tim16_ch1, eventout adc_in6 17 13 13 13 pa7 i/o tta spi1_mosi, i2s1_sd, tim3_ch2, tim14_ch1, tim1_ch1n, tim17_ch1, eventout adc_in7 18 14 14 - pb0 i/o tta tim3_ch3, tim1_ch2n, eventout adc_in8 19 15 15 14 pb1 i/o tta tim3_ch4, tim14_ch1, tim1_ch3n adc_in9 20 16 - - pb2 i/o ft 21 - - - pb10 i/o ftf tim2_ch3, i2c1_scl (3) 22 - - - pb11 i/o ftf tim2_ch4, eventout, i2c1_sda (3) 23 0 16 15 vss s ground 24 17 17 16 vdd s digital power supply 25 - - - pb12 i/o ft tim1_bkin, eventout, spi1_nss (3) 26 - - - pb13 i/o ft tim1_ch1n, spi1_sck (3) 27 - - - pb14 i/o ft tim1_ch2n, spi1_miso (3) 28 - - - pb15 i/o ft tim1_ch3n, spi1_mosi (3) rtc_refin table 8. pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp48 ufqfpn32 ufqfpn28 tssop20 alternate functions additional functions pinouts and pin description stm32f050xx 28/97 doc id 023683 rev 1 29 18 18 - pa8 i/o ft usart1_ck, tim1_ch1, eventout, mco 30 19 19 17 pa9 i/o ftf usart1_tx, tim1_ch2, i2c1_scl (3) 31 20 20 18 pa10 i/o ftf usart1_rx, tim1_ch3, tim17_bkin, i2c1_sda (3) 32 21 - - pa11 i/o ft usart1_cts, tim1_ch4, eventout 33 22 - - pa12 i/o ft usart1_rts, tim1_etr, eventout 34 23 21 19 pa 1 3 (swdat) i/o ft (4) ir_out, swdat 35 - - - pf6 i/o ftf i2c1_scl (3) 36 - - - pf7 i/o ftf i2c1_sda (3) 37 24 22 20 pa 1 4 (swclk) i/o ft (4) swclk, usart1_tx (3) 38 25 23 - pa15 i/o ft spi1_nss, i2s1_ws, tim2_ch_etr, eventout, usart1_rx (3) 39 26 24 - pb3 i/o ft spi1_sck, i2s1_ck, tim2_ch2, eventout 40 27 25 - pb4 i/o ft spi1_miso, i2s1_mck, tim3_ch1, eventout table 8. pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp48 ufqfpn32 ufqfpn28 tssop20 alternate functions additional functions stm32f050xx pinouts and pin description doc id 023683 rev 1 29/97 41 28 26 - pb5 i/o ft spi1_mosi, i2s1_sd, i2c1_smba, tim16_bkin, tim3_ch2 42 29 27 - pb6 i/o ftf i2c1_scl, usart1_tx, tim16_ch1n 43 30 28 - pb7 i/o ftf i2c1_sda, usart1_rx, tim17_ch1n 44 31 1 1 boot0 i b boot memory selection 45 32 - - pb8 i/o ftf i2c1_scl, tim16_ch1 46 - - - pb9 i/o ftf i2c1_sda, ir_out, tim17_ch1, eventout 47 0 - - vss s ground 48 1 - - vdd s digital power supply 1. pc13, pc14 and pc15 are supplied through the power switch. si nce the switch only sinks a limited amount of current (3 ma), the use of gpio pc13 to pc15 in output mode is limited: - the speed should not exceed 2 mhz with a maximum load of 30 pf - these gpios must not be used as a cu rrent sources (e.g. to drive an led). 2. after the first backup domain power-up, pc13, pc14 and pc15 operate as gpios. their function then depends on the content of the backup registers which is not reset by the main reset. for details on how to manage these gpios, refer to the battery backup domain and bkp register description sections in the stm32f05xx reference manual. 3. this alternate feature is available on standard dies only. 4. after reset, these pins are configur ed as swdat and swclk alternate functi ons, and the internal pull-up on swdat pin and internal pull-down on swclk pin are activated. table 8. pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp48 ufqfpn32 ufqfpn28 tssop20 alternate functions additional functions pinouts and pin description stm32f050xx 30/97 doc id 023683 rev 1 table 9. alternate functions selected through gpioa_afr registers for port a pin name af0 af1 af2 af3 af4 af5 af6 af7 pa0 usart1_cks (1) tim2_ch1_ etr pa1 eventout usart1_tx (1) tim2_ch2 pa2 usart1_rx (1) tim2_ch3 pa3 usart1_cts (1) tim2_ch4 pa 4 spi1_nss, i2s1_ws usart1_rts (1) tim14_ch1 pa 5 spi1_sck, i2s1_ck tim2_ch1_ etr pa 6 spi1_miso, i2s1_mck tim3_ch1 tim1_bkin tim16_ch1 eventout pa 7 spi1_mosi, i2s1_sd tim3_ch2 tim1_ch1n tim14_ch1 tim17_ch1 eventout pa8 mco usart1_ck tim1_ch1 eventout pa9 usart1_tx tim1_ch2 i2c1_scl (1) pa10 tim17_bkin usart1_rx tim1_ch3 i2c1_sda (1) pa11 eventout usart1_cts tim1_ch4 pa12 eventout usart1_rts tim1_etr pa 1 3 s w dat i r _ o u t pa14 swclk usart1_tx (1) pa 1 5 spi1_nss, i2s1_ws usart1_rx (1) tim2_ch1_ etr eventout 1. this alternate feature is available on standard dies only. stm32f050xx pinouts and pin description doc id 023683 rev 1 31/97 table 10. alternate functions selected through gpiob_afr registers for port b pin name af0 af1 af2 af3 pb0 eventout tim3_ch3 tim1_ch2n pb1 tim14_ch1 tim3_ch4 tim1_ch3n pb2 pb3 spi1_sck, i2s1_ck eventout tim2_ch2 pb4 spi1_miso, i2s1_mck tim3_ch1 eventout pb5 spi1_mosi, i2s1_sd tim3_c h2 tim16_bkin i2c1_smba pb6 usart1_tx i2c1_scl tim16_ch1n pb7 usart1_rx i2c1_sda tim17_ch1n pb8 i2c1_scl tim16_ch1 pb9 ir_out i2c1_sda tim17_ch1 eventout pb10 i2c1_scl (1) tim2_ch3 pb11 eventout i2c1_sda (1) tim2_ch4 pb12 spi1_nss (1) eventout tim1_bkin pb13 spi1_sck (1) tim1_ch1n pb14 spi1_miso (1) tim1_ch2n pb15 spi1_mosi (1) tim1_ch3n 1. this alternate feature is available on standard dies only. memory mapping stm32f050xx 32/97 doc id 023683 rev 1 5 memory mapping figure 7. stm32f050xx memory map 2 e s e r v e d ! ( " x & & & & & & & & 0 e r i p h e r a l s 3 2 ! - & l a s h m e m o r y r e s e r v e d r e s e r v e d 3 y s t e m m e m o r y / p t i o n b y t e s x % - 3 6 & l a s h s y s t e m m e m o r y o r 3 2 ! - d e p e n d i n g o n " / / 4 c o n f i g u r a t i o n x x % x # x ! x x x x x x x x & & & % # x & & & & x & & & & # x & & & & & & & x r e s e r v e d # / $ % ! 0 " ! 0 " r e s e r v e d x x x x r e s e r v e d x ! ( " x r e s e r v e d x & & x & & x x # o r t e x - i n t e r n a l p e r i p h e r a l s stm32f050xx memory mapping doc id 023683 rev 1 33/97 table 11. stm32f050x peripheral register boundary addresses bus boundary address size peripheral 0x4800 1800 - 0x5fff ffff ~384 mb reserved ahb2 0x4800 1400 - 0x4800 17ff 1kb gpiof 0x4800 1000 - 0x4800 13ff 1kb reserved 0x4800 0c00 - 0x4800 0fff 1kb reserved 0x4800 0800 - 0x4800 0bff 1kb gpioc 0x4800 0400 - 0x4800 07ff 1kb gpiob 0x4800 0000 - 0x4800 03ff 1kb gpioa 0x4002 4400 - 0x47ff ffff ~128 mb reserved ahb1 0x4002 4000 - 0x4002 43ff 1kb reserved 0x4002 3400 - 0x4002 3fff 3kb reserved 0x4002 3000 - 0x4002 33ff 1kb crc 0x4002 2400 - 0x4002 2fff 3kb reserved 0x4002 2000 - 0x4002 23ff 1kb flash interface 0x4002 1400 - 0x4002 1fff 3kb reserved 0x4002 1000 - 0x4002 13ff 1kb rcc 0x4002 0400 - 0x4002 0fff 3kb reserved 0x4002 0000 - 0x4002 03ff 1kb dma 0x4001 8000 - 0x4001 ffff 32kb reserved apb 0x4001 5c00 - 0x4001 7fff 9kb reserved 0x4001 5800 - 0x4001 5bff 1kb dbgmcu 0x4001 4c00 - 0x4001 57ff 3kb reserved 0x4001 4800 - 0x4001 4bff 1kb tim17 0x4001 4400 - 0x4001 47ff 1kb tim16 0x4001 4000 - 0x4001 43ff 1kb reserved 0x4001 3c00 - 0x4001 3fff 1kb reserved 0x4001 3800 - 0x4001 3bff 1kb usart1 0x4001 3400 - 0x4001 37ff 1kb reserved 0x4001 3000 - 0x4001 33ff 1kb spi1/i2s1 0x4001 2c00 - 0x4001 2fff 1kb tim1 0x4001 2800 - 0x4001 2bff 1kb reserved 0x4001 2400 - 0x4001 27ff 1kb adc 0x4001 0800 - 0x4001 23ff 7kb reserved 0x4001 0400 - 0x4001 07ff 1kb exti 0x4001 0000 - 0x4001 03ff 1kb syscfg 0x4000 8000 - 0x4000 ffff 32kb reserved memory mapping stm32f050xx 34/97 doc id 023683 rev 1 apb 0x4000 7c00 - 0x4000 7fff 1kb reserved 0x4000 7800 - 0x4000 7bff 1kb reserved 0x4000 7400 - 0x4000 77ff 1kb reserved 0x4000 7000 - 0x4000 73ff 1kb pwr 0x4000 5c00 - 0x4000 6fff 5kb reserved 0x4000 5800 - 0x4000 5bff 1kb reserved 0x4000 5400 - 0x4000 57ff 1kb i2c1 0x4000 4800 - 0x4000 53ff 3 kb reserved 0x4000 4400 - 0x4000 47ff 1kb reserved 0x4000 3c00 - 0x4000 43ff 2kb reserved 0x4000 3800 - 0x4000 3bff 1kb reserved 0x4000 3400 - 0x4000 37ff 1kb reserved 0x4000 3000 - 0x4000 33ff 1kb iwdg 0x4000 2c00 - 0x4000 2fff 1kb wwdg 0x4000 2800 - 0x4000 2bff 1kb rtc 0x4000 2400 - 0x4000 27ff 1kb reserved 0x4000 2000 - 0x4000 23ff 1kb tim14 0x4000 1400 - 0x4000 1fff 3kb reserved 0x4000 1000 - 0x4000 13ff 1kb reserved 0x4000 0800 - 0x4000 0fff 2kb reserved 0x4000 0400 - 0x4000 07ff 1kb tim3 0x4000 0000 - 0x4000 03ff 1kb tim2 table 11. stm32f050x peripheral register boundary addresses (continued) bus boundary address size peripheral stm32f050xx electrical characteristics doc id 023683 rev 1 35/97 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = v dda = 3.3 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 8 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 9 . figure 8. pin loading condition s figure 9. pin input voltage - 3 6 c = 50 pf - # 5 p i n - 3 6 - # 5 p i n 6 ) . electrical characteristics stm32f050xx 36/97 doc id 023683 rev 1 6.1.6 power supply scheme figure 10. power supply scheme caution: each power supply pair (v dd /v ss , v dda /v ssa etc.) must be decoupled with filtering ceramic capacitors as shown above. these capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the pcb to ensure the good functionality of the device. 6.1.7 current con sumption measurement figure 11. current consumption measurement scheme - 3 6 ! n a l o g 2 # s 0 , , 0 o w e r s w i t c h 6 " ! 4 ' 0 ) / s / 5 4 ) . + e r n e l l o g i c # 0 5 $ i g i t a l - e m o r i e s " a c k u p c i r c u i t r y , 3 % 2 4 # " a c k u p r e g i s t e r s 7 a k e u p l o g i c n & ? & 6 2 e g u l a t o r 6 $ $ ! 6 3 3 ! ! $ # $ ! # , e v e l s h i f t e r ) / , o g i c 6 $ $ n & ? & 6 $ $ ! 6 2 % & 6 2 % & 6 $ $ 6 3 3 - 3 6 6 " ! 4 6 $ $ 6 $ $ ! ) $ $ ) $ $ ! * % % @ 7 # " 5 stm32f050xx electrical characteristics doc id 023683 rev 1 37/97 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 12: voltage characteristics , table 13: current characteristics , and table 14: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 12. voltage characteristics (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. symbol ratings min max unit v dd ?v dda allowed voltage difference for v dd >v dda -0.4v v in (2) 2. v in maximum must always be respected. refer to table 13: current characteristics for the maximum allowed injected current values. input voltage on ft and ftf pins v ss ? 0.3 v dd + 4.0 v input voltage on tta pins v ss ? 0.3 4.0 v input voltage on any other pin v ss ? 0.3 4.0 v | v ddx | variations between different v dd power pins - 50 mv |v ssx ? v ss | variations between all the different ground pins -50mv v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.11: electrical sensitivity characteristics table 13. current characteristics symbol ratings max. unit i vdd( ) total current into sum of all vdd_x and vddsdx power lines (source) (1) 120 ma i vss( ) total current out of sum of all vss_x and vsssd ground lines (sink) (1) -120 i vdd(pin) maximum current into each vdd_ x or vddsdx power pin (source) (1) 100 i vss(pin) maximum current out of each vss_x or vsssd ground pin (sink) (1) -100 i io(pin) output current sunk by any i/o and control pin 25 output current source by any i/o and control pin - 25 i io(pin) total output current sunk by sum of all ios and control pins (2) 80 total output current sourced by sum of all ios and control pins (2) -80 i inj(pin) injected current on ft, ftf and b pins (3) -5/+0 injected current on tc and rst pin (4) 5 injected current on tta pins (5) 5 i inj(pin) total injected current (sum of all i/o and control pins) (6) 25 1. all main power (vdd, vdda) and ground (vss, vssa) pins must always be connected to the external power supply, in the permitted range. electrical characteristics stm32f050xx 38/97 doc id 023683 rev 1 2. this current consumption must be correc tly distributed over all i/os and control pi ns. the total output current must not be sunk/sourced between two consecut ive power supply pins referring to high pin count qfp packages. 3. positive injection is not possible on these i/os and does not occur for input voltages lower than the specified maximum value. 4. a positive injection is induced by v in >v dd while a negative injection is induced by v in electrical characteristics stm32f050xx 40/97 doc id 023683 rev 1 6.3.2 operating conditions at power-up / power-down the parameters given in ta bl e 1 6 are derived from tests performed under the ambient temperature condition summarized in ta b l e 1 5 . 6.3.3 embedded reset and power control block characteristics the parameter given in ta bl e 1 7 is derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 15: general operating conditions . table 16. operating conditions at power-up / power-down symbol parameter conditions min max unit t vdd v dd rise time rate 0 s/v v dd fall time rate 20 t vdda v dda rise time rate 0 v dda fall time rate 20 table 17. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v por/pdr (1) 1. the pdr detector monitors v dd and also v dda (if kept enabled in the opti on bytes). the por detector monitors only v dd . power on/power down reset threshold falling edge 1.8 (2) 2. the product behavior is guaranteed by design down to the minimum v por/pdr value. 1.88 1.96 v rising edge 1.84 1.92 2.0 v v pdrhyst (1) pdr hysteresis - 40 - mv t rsttempo (3) 3. guaranteed by design, not tested in production. reset temporization 1.5 2.5 4.5 ms table 18. programmable voltage detector characteristics symbol parameter conditions min (1) typ max (1) unit v pvd0 pvd threshold 0 rising edge 2.1 2.18 2.26 v falling edge 2 2.08 2.16 v v pvd1 pvd threshold 1 rising edge 2.19 2.28 2.37 v falling edge 2.09 2.18 2.27 v v pvd2 pvd threshold 2 rising edge 2.28 2.38 2.48 v falling edge 2.18 2.28 2.38 v v pvd3 pvd threshold 3 rising edge 2.38 2.48 2.58 v falling edge 2.28 2.38 2.48 v v pvd4 pvd threshold 4 rising edge 2.47 2.58 2.69 v falling edge 2.37 2.48 2.59 v stm32f050xx electrical characteristics doc id 023683 rev 1 41/97 6.3.4 embedded reference voltage the parameters given in ta bl e 1 9 are derived from tests performed under ambient temperature and v dd supply voltage condit ions summarized in table 15: general operating conditions . v pvd5 pvd threshold 5 rising edge 2.57 2.68 2.79 v falling edge 2.47 2.58 2.69 v v pvd6 pvd threshold 6 rising edge 2.66 2.78 2.9 v falling edge 2.56 2.68 2.8 v v pvd7 pvd threshold 7 rising edge 2.76 2.88 3 v falling edge 2.66 2.78 2.9 v v pvdhyst (2) pvd hysteresis - 100 - mv i dd(pvd) pvd current consumption - 0.15 0.26 a 1. data based on characterization results only, not tested in production. 2. guaranteed by design, not tested in production. table 18. programmable voltage detector characteristics (continued) symbol parameter conditions min (1) typ max (1) unit table 19. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.16 1.2 1.25 v ?40 c < t a < +85 c 1.16 1.2 1.24 (1) 1. data based on characterization results, not tested in production. v t s_vrefint (2) 2. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the internal reference voltage - 5.1 17.1 (3) 3. guaranteed by design, not tested in production. s v refint internal reference voltage spread over the temperature range v dda = 3 v 10 mv - - 10 (3) mv t coeff temperature coefficient - - 100 (3) ppm/c electrical characteristics stm32f050xx 42/97 doc id 023683 rev 1 6.3.5 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pin loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 11: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to coremark code. the data provided apply to standard dies only. typical and maximum current consumption the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load) all peripherals are disabled except when explicitly mentioned the flash memory access time is adjusted to the f hclk frequency (0 wait state from 0 to 24 mhz and 1 wait state above 24 mhz) prefetch is on when the peripherals are enabled, otherwise it is off (to enable prefetch the prftbe bit in the flash_acr register must be set before clock setting and bus prescaling) when the peripherals are enabled f pclk = f hclk the parameters given in ta bl e 2 0 to ta bl e 2 6 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 15: general operating conditions . stm32f050xx electrical characteristics doc id 023683 rev 1 43/97 table 20. typical and maximum current consumption from v dd supply at v dd = 3.6 symbol parameter conditions f hclk all peripherals enabled a ll peripherals disabled unit typ max @ t a(1) typ max @ t a(1) 25 c 85 c 105 c 25 c 85 c 105 c idd supply current in run mode, executing from flash external clock (hse bypass) 48 mhz 18.4 20.0 20.1 20.4 11.4 12.5 12.5 12.6 ma 32 mhz 12.4 13.2 13.2 13.8 7.9 8.3 8.5 8.6 24 mhz 9.9 10.7 10.7 11.0 6.2 6.8 7.0 7.0 8 mhz 3.3 3.6 3.8 3.9 2.2 2.6 2.6 2.6 1 mhz 0.8 1.1 1.1 1.1 0.7 0.9 0.9 0.9 internal clock (hsi) 48 mhz 18.9 20.9 21.1 21.5 11.7 12.3 12.9 13.1 32 mhz 12.8 13.7 14.2 14.8 8.0 8.7 9.1 9.1 24 mhz 9.7 10.4 11.2 11.3 6.1 6.5 6.7 6.9 8 mhz 3.5 4.0 4.0 4.1 2.4 2.6 2.7 2.7 supply current in run mode, executing from ram external clock (hse bypass) 48 mhz 17.3 19.7 19.8 20.0 10.3 11.2 11.3 11.7 32 mhz 11.2 12.5 12.7 12.7 6.7 7.3 7.6 7.6 24 mhz 8.9 10.0 10.1 10.2 5.1 5.5 5.8 5.9 8 mhz 2.8 3.1 3.3 3.4 1.7 2.0 2.1 2.1 1 mhz 0.3 0.6 0.6 1.3 0.2 0.5 0.8 0.8 internal clock (hsi) 48 mhz 17.4 19.7 20.0 20.2 10.4 11.2 11.3 11.8 32 mhz 11.8 12.8 13.1 13.3 6.8 7.4 7.7 7.9 24 mhz 9.0 10.0 10.1 10.2 5.2 5.7 6.0 6.0 8 mhz 3.0 3.2 3.5 3.6 1.8 2.0 2.2 2.2 supply current in sleep mode, executing from flash or ram external clock (hse bypass) 48 mhz 10.7 11.7 11.9 12.5 2.4 2.6 2.7 2.9 32 mhz 7.1 7.8 8.1 8.2 1.6 1.7 1.9 1.9 24 mhz 5.5 6.3 6.4 6.4 1.3 1.4 1.5 1.5 8 mhz 1.8 2.0 2.0 2.1 0.4 0.4 0.5 0.5 1 mhz 0.2 0.5 0.5 0.5 0.1 0.1 0.1 0.1 internal clock (hsi) 48 mhz 10.8 11.9 12.1 12.6 2.4 2.7 2.7 2.9 32 mhz 7.3 8.0 8.4 8.5 1.7 1.9 1.9 2.0 24 mhz 5.5 6.2 6.5 6.5 1.3 1.5 1.5 1.6 8 mhz 1.9 2.2 2.3 2.4 0.5 0.5 0.5 0.6 electrical characteristics stm32f050xx 44/97 doc id 023683 rev 1 table 21. typical and maximum current consumption from the v dda supply symbol parameter conditions (1) f hclk v dda = 2.4 v v dda = 3.6 v unit typ max @ t a (2) typ max @ t a (2) 25 c 85 c 105 c 25 c 85 c 105 c i dda supply current in run mode, code executing from flash or ram hse bypass, pll on 48 mhz 150 170 178 182 164 183 195 198 a 32 mhz 104 121 126 128 113 129 135 138 24 mhz 82 96 100 103 88 102 106 108 hse bypass, pll off 8 mhz 2.0 2.7 3.1 3.3 3.5 3.8 4.1 4.4 1 mhz 2.0 2.7 3.1 3.3 3.5 3.8 4.1 4.4 hsi clock, pll on 48 mhz 220 240 248 252 244 263 275 278 32 mhz 174 191 196 198 193 209 215 218 24 mhz 152 167 173 174 168 183 190 192 hsi clock, pll off 8 mhz 72 79 82 83 83.5 91 94 95 supply current in sleep mode, code executing from flash or ram hse bypass, pll on 48 mhz 150 170 178 182 164 183 195 198 32 mhz 104 121 126 128 113 129 135 138 24 mhz 82 96 100 103 88 102 106 108 hse bypass, pll off 8 mhz 2.0 2.7 3.1 3.3 3.5 3.8 4.1 4.4 1 mhz 2.0 2.7 3.1 3.3 3.5 3.8 4.1 4.4 hsi clock, pll on 48 mhz 220 240 248 252 244 263 275 278 32 mhz 174 191 196 198 193 209 215 218 24 mhz 152 167 173 174 168 183 190 192 hsi clock, pll off 8 mhz 72 79 82 83 83.5 91 94 95 1. current consumption from the v dda supply is independent of whether the perip herals are on or off. furthermore when the pll is off, i dda is independent from the frequency. 2. data based on characterization results, not tested in production. stm32f050xx electrical characteristics doc id 023683 rev 1 45/97 upply current table 22. typical and maximum v dd consumption in stop and standby modes symbol parameter conditions typ @v dd (v dd = v dda )max (1) unit 2.0 v 2.4 v 2.7 v 3.0 v 3.3 v 3.6 v t a = 25 c t a = 85 c t a = 105 c i dd supply current in stop mode regulator in run mode, all oscillators off 15 15.1 15.25 15.45 15.7 16 18 (2) 38 55 (2) a regulator in low-power mode, all oscillators off 3.15 3.25 3.35 3.45 3.7 4 5.5 (2) 22 41 (2) supply current in standby mode lsi on and iwdg on 0.8 0.95 1.05 1.2 1.35 1.5 - - - lsi off and iwdg off 0.65 0.75 0.85 0.95 1.1 1.3 2 (2) 2.5 3 (2) 1. data based on characterization results, not tested in production unless otherwise specified. 2. data based on characterization results and tested in production. table 23. typical and maximum v dda consumption in stop and standby modes symbol parameter conditions typ @v dd (v dd = v dda )max (1) unit 2.0 v 2.4 v 2.7 v 3.0 v 3.3 v 3.6 v t a = 25 c t a = 85 c t a = 105 c i dda supply current in stop mode v dda monitoring on regulator in run mode, all oscillators off 1.85 2 2.15 2.3 2.45 2.6 3.5 3.5 4.5 a regulator in low-power mode, all oscillators off 1.85 2 2.15 2.3 2.45 2.6 3.5 3.5 4.5 supply current in standby mode lsi on and iwdg on 2.25 2.5 2.65 2.85 3.05 3.3 - - - lsi off and iwdg off 1.75 1.9 2 2.15 2.3 2.5 3.5 3.5 4.5 supply current in stop mode v dda monitoring off regulator in run mode, all oscillators off 1.11 1.15 1.18 1.22 1.27 1.35 - - - regulator in low-power mode, all oscillators off 1.11 1.15 1.18 1.22 1.27 1.35 - - - supply current in standby mode lsi on and iwdg on 1.5 1.58 1.65 1.78 1.91 2.04 - - - lsi off and iwdg off 1 1.02 1.05 1.05 1.15 1.22 - - - 1. data based on characterization results, not tested in production. electrical characteristics stm32f050xx 46/97 doc id 023683 rev 1 typical current consumption the mcu is placed under the following conditions: v dd =v dda =3.3 v all i/o pins are in analog input configuration the flash access time is adjusted to f hclk frequency (0 wait states from 0 to 24 mhz, 1 wait state above) prefetch is on when the peripherals are enabled, otherwise it is off when the peripherals are enabled, f pclk = f hclk pll is used for frequencies greater than 8 mhz ahb prescaler of 2, 4, 8 and 16 is used for the frequencies 4 mhz, 2 mhz, 1 mhz and 500 khz respectively a development tool is connected to the board and the parasitic pull-up current is around 30 a table 24. typical and maximum current consumption from v bat supply symbol parameter conditions typ @ v bat max (1) unit = 1.65 v = 1.8 v = 2.4 v = 2.7 v = 3.3 v = 3.6 v t a = 25 c t a = 85 c t a = 105 c i dd _ vbat backup domain supply current lse & rtc on; ?xtal mode?: lower driving capability; lsedrv[1:0] = '00' 0.41 0.43 0.53 0.58 0.71 0.80 0.85 1.1 1.5 a lse & rtc on; ?xtal mode? higher driving capability; lsedrv[1:0] = '11' 0.71 0.75 0.85 0.91 1.06 1.16 1.25 1.55 2 1. data based on characterization results, not tested in production. stm32f050xx electrical characteristics doc id 023683 rev 1 47/97 table 25. typical current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk typ unit peripherals enabled peripherals disabled i dd supply current in run mode from v dd supply running from hse crystal clock 8 mhz, code executing from flash 48 mhz 18.4 11.4 ma 36 mhz 13.9 8.9 32 mhz 12.4 7.9 24 mhz 9.9 6.2 16 mhz 6.6 4.3 8 mhz 3.3 2.2 4 mhz 1.7 1.6 2 mhz 1.3 1.2 1 mhz 0.8 0.7 500 khz 0.6 0.6 i dda supply current in run mode from v dda supply 48 mhz 140 140 a 36 mhz 109 109 32 mhz 96 96 24 mhz 76 76 16 mhz 51 51 8 mhz 1.7 1.7 4 mhz 1.6 1.6 2 mhz 1.5 1.5 1 mhz 1.1 1.1 500 khz 1.1 1.1 electrical characteristics stm32f050xx 48/97 doc id 023683 rev 1 table 26. typical current consumption in sleep mode, code running from flash or ram symbol parameter conditions f hclk typ unit peripherals enabled peripherals disabled i dd supply current in sleep mode from v dd supply running from hse crystal clock 8 mhz, code executing from flash or ram 48 mhz 10.7 2.4 ma 36 mhz 8.1 1.8 32 mhz 7.1 1.6 24 mhz 5.5 1.3 16 mhz 3.7 0.9 8 mhz 1.9 0.5 4 mhz 1.5 0.4 2 mhz 1.1 0.3 1 mhz 0.8 0.3 500 khz 0.6 0.3 125 khz 0.5 0.3 i dda supply current in sleep mode from v dda supply 48 mhz 140 140 a 36 mhz 109 109 32 mhz 96 96 24 mhz 76 76 16 mhz 51 51 8 mhz 1.7 1.7 4 mhz 1.6 1.6 2 mhz 1.5 1.5 1 mhz 1.1 1.1 500 khz 1.1 1.1 125 khz 1.1 1.1 stm32f050xx electrical characteristics doc id 023683 rev 1 49/97 i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up generate current consumption when the pin is externally held low. the value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in table 45: i/o static characteristics . for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally applied. this current consumption is caused by the input schmitt trigger circuits used to discriminate the input value. unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog inputs. caution: any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by using pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral current consumption measured previously (see table 28: peripheral current consumption ), the i/os used by an application also contribute to the current consumption. when an i/o pin switches, it uses the current from the mcu supply voltage to supply the i/o pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: where i sw is the current sunk by a switching i/o to charge/discharge the capacitive load v dd is the mcu supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext + c s c s is the pcb board capacita nce including the pad pin. the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. i sw v dd f sw c = electrical characteristics stm32f050xx 50/97 doc id 023683 rev 1 table 27. switching output i/o current consumption symbol parameter conditions (1) 1. c s = 7 pf (estimated value). i/o toggling frequency (f sw ) typ unit i sw i/o current consumption v dd = 3.3 v c =c int 4 mhz 0.07 ma 8 mhz 0.15 16 mhz 0.31 24 mhz 0.53 48 mhz 0.92 v dd = 3.3 v c ext = 0 pf c = c int + c ext + c s 4 mhz 0.18 8 mhz 0.37 16 mhz 0.76 24 mhz 1.39 48 mhz 2.188 v dd = 3.3 v c ext = 10 pf c = c int + c ext + c s 4 mhz 0.32 8 mhz 0.64 16 mhz 1.25 24 mhz 2.23 48 mhz 4.442 v dd = 3.3 v c ext = 22 pf c = c int + c ext + c s 4 mhz 0.49 8 mhz 0.94 16 mhz 2.38 24 mhz 3.99 v dd = 3.3 v c ext = 33 pf c = c int + c ext + c s 4 mhz 0.64 8 mhz 1.25 16 mhz 3.24 24 mhz 5.02 v dd = 3.3 v c ext = 47 pf c = c int + c ext + c s c = c int 4 mhz 0.81 8 mhz 1.7 16 mhz 3.67 v dd = 2.4 v c ext = 47 pf c = c int + c ext + c s c = c int 4 mhz 0.66 8 mhz 1.43 16 mhz 2.45 24 mhz 4.97 stm32f050xx electrical characteristics doc id 023683 rev 1 51/97 on-chip peripheral current consumption the current consumption of the on-chip peripherals is given in ta bl e 2 8 . the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ambient operating temperature and v dd supply voltage conditions summarized in table 12: voltage characteristics table 28. peripheral current consumption peripheral typical consumption at 25 c unit i dd i dda adc (1) 1. adc is in ready state after setting the aden bit in the adc_cr register (adrdy bit in adc_isr is high). 0.53 0.964 ma crc 0.10 - dbgmcu 0.18 - dma 0.35 - gpioa 0.48 - gpiob 0.58 - gpioc 0.12 - gpiof 0.06 - i2c1 0.43 - pwr 0.22 - spi1/i2s1 0.63 - syscfg 0.28 tim1 1.01 - tim2 1.00 - tim3 0.78 - tim6 0.32 - tim14 0.45 - tim16 0.57 - tim17 0.59 - usart1 1.07 - wwdg 0.22 - electrical characteristics stm32f050xx 52/97 doc id 023683 rev 1 6.3.6 external cloc k source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillator is switched off and the input pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.13 . however, the recommended clock input waveform is shown in figure 12: high-speed external clock source ac timing diagram . figure 12. high-speed external clock source ac timing diagram table 29. high-speed external user clock characteristics symbol parameter (1) 1. guaranteed by design, not tested in production. conditions min typ max unit f hse_ext user external clock source frequency 1832mhz v hseh osc_in input pin high level voltage 0.7v dd -v dd v v hsel osc_in input pin low level voltage v ss -0.3v dd t w(hseh) t w(hsel) osc_in high or low time 15 - - ns t r(hse) t f(hse) osc_in rise or fall time - - 20 - 3 6 6 ( 3 % ( t f ( 3 % 4 ( 3 % t t r ( 3 % 6 ( 3 % , t 7 ( 3 % ( t 7 ( 3 % , stm32f050xx electrical characteristics doc id 023683 rev 1 53/97 low-speed external user clock generated from an external source in bypass mode the lse oscilla tor is switched off and the in put pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.13 . however, the recommended clock input waveform is shown in figure 13 . figure 13. low-speed external clock source ac timing diagram table 30. low-speed external user clock characteristics symbol parameter (1) 1. guaranteed by design, not tested in production. conditions min typ max unit f lse_ext user external clock source frequency - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss -0.3v dd t w(lseh) t w(lsel) osc32_in high or low time 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time - - 50 - 3 6 6 , 3 % ( t f , 3 % 4 , 3 % t t r , 3 % 6 , 3 % , t 7 , 3 % ( t 7 , 3 % , electrical characteristics stm32f050xx 54/97 doc id 023683 rev 1 high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 32 mhz crystal/ceramic resonator oscillator. all the information given in this pa ragraph are base d on design simulation results obtained with typi cal external components specified in ta b l e 3 1 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 20 pf range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see figure 14 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . note: for information on electing the crystal, refer to the applicatio n note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. table 31. hse oscillator characteristics symbol parameter conditions (1) 1. resonator characte ristics given by the crystal/ ceramic resonator manufacturer. min (2) typ max (2) 2. guaranteed by design, not tested in production. unit f osc_in oscillator frequency 4 8 32 mhz r f feedback resistor - 200 - k i dd hse current consumption during startup (3) 3. this consumption level occurs during the first 2/3 of the t su(hse) startup time -8.5 ma v dd =3.3 v, rm= 30 , cl=10 pf@8 mhz -0.4- v dd =3.3 v, rm= 45 , cl=10 pf@8 mhz -0.5- v dd =3.3 v, rm= 30 , cl=5 pf@32 mhz -0.8- v dd =3.3 v, rm= 30 , cl=10 pf@32 mhz -1- v dd =3.3 v, rm= 30 , cl=20 pf@32 mhz -1.5- g m oscillator transconductance startup 10 - - ma/v t su(hse) (4) 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonat or and it can vary significantly with the crystal manufacturer startup time v dd is stabilized - 2 - ms stm32f050xx electrical characteristics doc id 023683 rev 1 55/97 figure 14. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal resonator oscillator. all the information given in this pa ragraph are based on de sign simulation results obtained with typica l external components specified in ta bl e 3 2 . in the application, the resonator and the load capacitors have to be placed as clos e as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). note: for information on selecting the crystal, refer to the app lication note an 2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. - 3 6 / 3 # ? / 5 4 / 3 # ? ) . f ( 3 % # , 2 & - ( z r e s o n a t o r 2 % 8 4 # , 2 e s o n a t o r w i t h i n t e g r a t e d c a p a c i t o r s " i a s c o n t r o l l e d g a i n table 32. lse oscillator characteristics (f lse = 32.768 khz) symbol parameter conditions (1) min (2) typ max (2) unit i dd lse current consumption lsedrv[1:0]=00 lower driving capability -0.50.9 a lsedrv[1:0]= 01 medium low driving capability --1 lsedrv[1:0] = 10 medium high driving capability --1.3 lsedrv[1:0]=11 higher driving capability --1.6 g m oscillator transconductance lsedrv[1:0]=00 lower driving capability 5- - a/v lsedrv[1:0]= 01 medium low driving capability 8- - lsedrv[1:0] = 10 medium high driving capability 15 - - lsedrv[1:0]=11 higher driving capability 25 - - t su(lse) (3) startup time v dd is stabilized - 2 - s 1. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. 2. guaranteed by design, not tested in production. 3. t su(lse) is the startup time measured from the moment it is enab led (by software) to a stabili zed 32.768 khz oscillation is reached. this value is measured for a standard crystal and it can vary significantly wi th the crystal manufacturer electrical characteristics stm32f050xx 56/97 doc id 023683 rev 1 figure 15. typical application with a 32.768 khz crystal note: an external resistor is not required between osc32_in and osc32_out and it is forbidden to add one. - 3 6 / 3 # ? / 5 4 / 3 # ? ) . f , 3 % # , k ( z r e s o n a t o r # , 2 e s o n a t o r w i t h i n t e g r a t e d c a p a c i t o r s $ r i v e p r o g r a m m a b l e a m p l i f i e r stm32f050xx electrical characteristics doc id 023683 rev 1 57/97 6.3.7 internal clock source characteristics the parameters given in ta bl e 3 3 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 15: general operating conditions . the provided curves are characterization results, not tested in production. high-speed internal (hsi) rc oscillator figure 16. hsi oscillator accuracy characterization results table 33. hsi oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency - 8 mhz trim hsi user trimming step - - 1 (2) 2. guaranteed by design, not tested in production. % ducy (hsi) duty cycle 45 (2) -55 (2) % acc hsi accuracy of the hsi oscillator (factory calibrated) t a = ?40 to 105 c ?3.8 (3) 3. data based on characterization results, not tested in production. -4.6 (3) % t a = ?10 to 85 c ?2.9 (3) -2.9 (3) % t a = 0 to 70 c ?2.3 (3) -2.2 (3) % t a = 25 c ?1 - 1 % t su(hsi) hsi oscillator startup time 1 (2) -2 (2) s i dda(hsi) hsi oscillator power consumption - 80 100 (2) a - 3 6 - ! 8 - ) . 4 ! ; ? # = electrical characteristics stm32f050xx 58/97 doc id 023683 rev 1 high-speed internal 14 mhz (hsi14) rc oscillator (dedicated to adc) figure 17. hsi14 oscillator accuracy characterization results table 34. hsi14 oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi14 frequency - 14 mhz trim hsi14 user-trimming step - - 1 (2) 2. guaranteed by design, not tested in production. % ducy (hsi14) duty cycle 45 (2) -55 (2) % acc hsi14 accuracy of the hsi14 oscillator (factory calibrated) t a = ?40 to 105 c ?4.2 (3) 3. data based on characterization results, not tested in production. -5.1 (3) % t a = ?10 to 85 c ?3.2 (3) -3.1 (3) % t a = 0 to 70 c ?2.5 (3) -2.3 (3) % t a = 25 c ?1 - 1 % t su(hsi14) hsi14 oscillator startup time 1 (2) -2 (2) s i dda(hsi14) hsi14 oscillator power consumption -100150 (2) a - 3 6 - ! 8 - ) . 4 ! ; ? # = stm32f050xx electrical characteristics doc id 023683 rev 1 59/97 low-speed internal (lsi) rc oscillator wakeup time from low-power mode the wakeup times given in ta b l e 3 6 is measured on a wakeup phase with a 8-mhz hsi rc oscillator. the event used to wake up the de vice depends from the current operating mode: stop or sleep mode: the wakeup event is wfe. the wakeup pin used in sleep, stop and standby modes is pa0. all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 15: general operating conditions . table 35. lsi oscillator characteristics (1) 1. v dda = 3.3 v , t a = ?40 to 105 c unless otherwise specified. symbol parameter min typ max unit f lsi frequency 30 40 50 khz t su(lsi) (2) 2. guaranteed by design, not tested in production. lsi oscillator startup time - - 85 s i dda(lsi) (2) lsi oscillator power consumption - 0.75 1.2 a table 36. low-power mode wakeup timings symbol parameter conditions typ @v dd max unit = 2.0 v = 2.4 v = 2.7 v = 3 v = 3.3 v t wustop wakeup from stop mode regulator in run mode 4.24.24.24.24.25 s regulator in low power mode 8.05 7.05 6.6 6.27 6.05 9 t wustandby wakeup from standby mode 60.35 55.6 53.5 52.02 50.96 t wusleep wakeup from sleep mode 1.11.11.11.11.1 electrical characteristics stm32f050xx 60/97 doc id 023683 rev 1 6.3.8 pll characteristics the parameters given in ta bl e 3 7 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 15: general operating conditions . table 37. pll characteristics symbol parameter value unit min typ max f pll_in pll input clock (1) 1. take care to use the appropriate multiplier factors to obtain pll input clock values compatible with the range defined by f pll_out . 1 (2) 8.0 24 (2) mhz pll input clock duty cycle 40 (2) -60 (2) % f pll_out pll multiplier output clock 16 (2) -48mhz t lock pll lock time - - 200 (2) 2. guaranteed by design, not tested in production. s jitter pll cycle-to-cycle jitter - - 300 (2) ps stm32f050xx electrical characteristics doc id 023683 rev 1 61/97 6.3.9 memory characteristics flash memory the characteristics are given at t a = ?40 to 105 c unless otherwise specified. 6.3.10 emc characteristics susceptibility tests ar e performed on a sample basis during device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on the device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure occurs. the failure is indicated by the leds: electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in ta b l e 4 0 . they are based on the ems levels and classes defined in application note an1709. table 38. flash memory characteristics symbol parameter conditions min typ max (1) 1. guaranteed by design, not tested in production. unit t prog 16-bit programming time t a = ?40 to +105 c 40 53.5 60 s t erase page (1 kb) erase time t a = ?40 to +105 c 20 - 40 ms t me mass erase time t a = ?40 to +105 c 20 - 40 ms i dd supply current write mode - - 10 ma erase mode - - 12 ma table 39. flash memory endurance and data retention symbol parameter conditions value unit min (1) 1. data based on characterization results, not tested in production. n end endurance t a = ?40 to +85 c (6 suffix versions) t a = ?40 to +105 c (7 suffix versions) 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over t he whole temperature range. 30 ye a r s 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20 electrical characteristics stm32f050xx 62/97 doc id 023683 rev 1 designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o ports). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. table 40. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, lqfp64, t a = +25 c, f hclk = 48 mhz conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, lqfp64, t a = +25 c, f hclk = 48 mhz conforms to iec 61000-4-4 3b table 41. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8/48 mhz s emi peak level v dd = 3.6 v, t a = 25 c, lqfp64 package compliant with iec 61967-2 0.1 to 30 mhz -3 dbv 30 to 130 mhz 28 130 mhz to 1ghz 23 sae emi level 4 - stm32f050xx electrical characteristics doc id 023683 rev 1 63/97 6.3.11 electrical sensi tivity characteristics based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determine its perfor mance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. static latch-up two complementary static tests are required on six parts to assess the latch-up performance: a supply overvoltage is applied to each power supply pin a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latch-up standard. 6.3.12 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection a ccidentally happens, susceptibilit y tests are performed on a sample basis during device characterization. functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode. while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (more than 5 lsb tue), out of conventional limits of current injection on adjacent pins (more than ?5 a) or other functional failure (reset occurrence or oscilla tor frequency deviation, for example). table 42. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c, conforming to jesd22-a114 22000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c, conforming to jesd22-c101 ii 500 table 43. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +105 c conforming to jesd78a ii level a electrical characteristics stm32f050xx 64/97 doc id 023683 rev 1 the characterization results are given in ta b l e 4 4 . table 44. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot0 ?0 na ma injected current on all ft and ftf pins with induced leakage current on adjacent pins less than ?5 a ?5 na injected current on all tta pins with induced leakage current on adjacent pins less than ?5 a ?5 +5 injected current on all tc & reset pins with induced leakage current on adjacent pins less than ?5 a ?5 +5 stm32f050xx electrical characteristics doc id 023683 rev 1 65/97 6.3.13 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in ta bl e 4 5 are derived from tests performed under the conditions summarized in table 15: general operating conditions . all i/os are cmos and ttl compliant. table 45. i/o static characteristics symbol parameter conditions min typ max unit v il low level input voltage tc and tta i/o - - 0.3 v dd +0.07 (1) v ft and ftf i/o - - 0.475 v dd ?0.2 (1) boot0 - - 0.3 v dd ?0.3 (1) all i/os except boot0 pin - - 0.3 v dd v ih high level input voltage tc and tta i/o 0.445 v dd +0.398 (1) -- v ft and ftf i/o 0.5 v dd +0.2 (1) -- boot0 0.2 v dd +0.95 (1) -- all i/os except boot0 pin 0.7 v dd -- v hys schmitt trigger hysteresis tc and tta i/o - 200 (1) - mv ft and ftf i/o - 100 (1) - boot0 - 300 (1) - i lkg input leakage current (2) v ss v in v dd i/o tc, ft and ftf -- 0 . 1 a v ss v in v dd 2 v v dd v dda 3.6 v i/o tta used in digital mode -- 0 . 1 v in = 5 v i/o ft and ftf --10 v in = 3.6 v , 2 v v dd v in v dda = 3.6 v i/o tta used in digital mode --1 v ss v in v dda 2 v v dd v dda 3.6 v i/o tta used in analog mode -- 0 . 2 r pu weak pull-up equivalent resistor (3) v in = v ss 25 40 55 k electrical characteristics stm32f050xx 66/97 doc id 023683 rev 1 r pd weak pull-down equivalent resistor (3) v in = v dd 25 40 55 k c io i/o pin capacitance -5-pf 1. data based on design simulati on only. not tested in production. 2. leakage could be higher than maximum value, if negative current is injected on adjacent pins. 3. pull-up and pull-down resistor s are designed with a true resistance in seri es with a switchable pmos/nmos. this mos/nmos contribution to the series resistance is minimum (~10% order) . table 45. i/o static characteristics (continued) symbol parameter conditions min typ max unit stm32f050xx electrical characteristics doc id 023683 rev 1 67/97 all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements is shown in figure 18 and figure 19 for standard i/os, and in figure 20 and figure 21 for 5 v tolerant i/os. the following curves are design simulation results, not tested in production. figure 18. tc and tta i/o input characteristics - cmos port figure 19. tc and tta i/o input characteristics - ttl port ms30255v1 v dd (v) v ihmin 2.0 v ilmax 0.7 v il /v ih (v) 1.3 2.0 3.6 cmos standard requirements v ihmin = 0.7v dd v ilmax = 0.3v dd +0.07 0.6 2.7 3.0 3.3 cmos standard requirements v ilmax = 0.3v dd v ihmin = 0.445v dd +0.398 input range not guaranteed ms30256v1 v dd (v) v ihmin 2.0 v ilmax 0.8 v il /v ih (v) 1.3 2.0 3.6 ttl standard requirements v ihmin = 2 v v ilmax = 0.3v dd +0.07 0.7 2.7 3.0 3.3 ttl standard requirements v ilmax = 0.8 v v ihmin = 0.445v dd +0.398 input range not guaranteed electrical characteristics stm32f050xx 68/97 doc id 023683 rev 1 figure 20. five volt tolerant (ft and ftf) i/o input characteristics - cmos port figure 21. five volt tolerant (ft and ftf) i/o input characteristics - ttl port ms30257v1 v dd (v) 2.0 v il /v ih (v) 1.0 2.0 3.6 cmos standard requirements v ih min = 0.7v dd v ilmax = 0.475v dd -0.2 0.5 cmos standard requirements v ilmax = 0.3v dd v ihmin = 0.5v dd +0.2 input range not guaranteed ms30258v1 v dd (v) 2.0 v il /v ih (v) 1.0 2.0 3.6 v ilmin = 0.475v dd -0.2 0.5 v ihmin = 0.5v dd +0.2 input range not guaranteed 2.7 ttl standard requirements v ihmin = 2 v ttl standard requirements v ilmax = 0.8 v 0.8 stm32f050xx electrical characteristics doc id 023683 rev 1 69/97 output driving current the gpios (general purpose input/outputs) can sink or source up to +/-8 ma, and sink or source up to +/- 20 ma (with a relaxed v ol/ v oh ). in the user application, the number of i/o pins which can drive current must be limited to respect the absolute maxi mum rating specified in section 6.2 : the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see table 13: current characteristics ). the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see table 13: current characteristics ). output voltage levels unless otherwise specified, the parameters given in ta bl e 4 6 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 15: general operating conditions . all i/os are cmos and ttl compliant (ft, tta or tc unless otherwise specified). table 46. output voltage characteristics symbol parameter conditions min max unit v ol (1) 1. the i io current sunk by the device must always re spect the absolute maximum rating specified in table 13: current characteristics and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin cmos port (2) i io = +8 ma 2.7 v < v dd < 3.6 v 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. -0.4 v v oh (3) 3. the i io current sourced by the device must always re spect the absolute maximum rating specified in table 13: current characteristics and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin v dd ?0.4 - v ol (1) output low level voltage for an i/o pin ttl port (2) i io =+ 8ma 2.7 v < v dd < 3.6 v -0.4 v v oh (3) output high level voltage for an i/o pin 2.4 - v ol (1)(4) 4. data based on design simulati on only. not tested in production. output low level voltage for an i/o pin i io = +20 ma 2.7 v < v dd < 3.6 v -1.3 v v oh (3)(4) output high level voltage for an i/o pin v dd ?1.3 - v ol (1)(4) output low level voltage for an i/o pin i io = +6 ma 2 v < v dd < 2.7 v -0.4 v v oh (3)(4) output high level voltage for an i/o pin v dd ?0.4 - v olfm+ (1) output low level voltage for an ftf i/o pin in fm+ mode i io = +20 ma 2.7 v < v dd < 3.6 v -0.4v electrical characteristics stm32f050xx 70/97 doc id 023683 rev 1 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 22 and ta bl e 4 7 , respectively. unless otherwise specified, the parameters given are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 15: general operating conditions . table 47. i/o ac characteristics (1) ospeedry [1:0] value (1) symbol parameter conditions min max unit x0 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v - 2 mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v -125 (3) ns t r(io)out output low to high level rise time -125 (3) 01 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v - 10 mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v -25 (3) ns t r(io)out output low to high level rise time -25 (3) 11 f max(io)out maximum frequency (2) c l = 30 pf, v dd = 2.7 v to 3.6 v - 50 mhz c l = 50 pf, v dd = 2.7 v to 3.6 v - 30 c l = 50 pf, v dd = 2 v to 2.7 v - 20 t f(io)out output high to low level fall time c l = 30 pf, v dd = 2.7 v to 3.6 v - 5 (3) ns c l = 50 pf, v dd = 2.7 v to 3.6 v - 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v - 12 (3) t r(io)out output low to high level rise time c l = 30 pf, v dd = 2.7 v to 3.6 v - 5 (3) c l = 50 pf, v dd = 2.7 v to 3.6 v - 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v - 12 (3) fm+ configuration (4) f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v - 2 (3) mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v - 12 (3) ns t r(io)out output low to high level rise time c l = 50 pf, v dd = 2 v to 3.6 v - 34 (3) t extipw pulse width of external signals detected by the exti controller 10 - ns 1. the i/o speed is configured using the ospeedrx[1:0] bits . refer to the rm0091 reference manual for a description of gpio port configuration register. 2. the maximum frequency is defined in figure 22 . 3. guaranteed by design, not tested in production. 4. when fm+ configuration is set, the i/o speed control is bypassed. refer to the stm32f05xxx reference manual rm0091 for a detailed description of fm+ i/o configuration. stm32f050xx electrical characteristics doc id 023683 rev 1 71/97 figure 22. i/o ac characteristics definition 6.3.14 nrst pin characteristics the nrst pin input driver uses cmos techno logy. it is connected to a permanent pull-up resistor, r pu (see table 45: i/o static characteristics ). unless otherwise specified, the parameters given in ta bl e 4 8 are derived from tests performed under ambient temperature and vdd supply voltage conditions summarized in table 15: general operating conditions . figure 23. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 48 . otherwise the reset will not be taken into account by the device. ai14131 10% 90% 50% t r(io)out output ext ernal on 50pf maximum frequency is achieved if (t r + t f ) 2/3)t and if the duty cycle is (45-55%) 10 % 50% 90% when loaded by 50pf t t r(io)out table 48. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) (1) 1. guaranteed by design, not tested in production. nrst input low level voltage ?0.3 - 0.8 v v ih(nrst) (1) nrst input high level voltage 2 - v dd +0.3 v hys(nrst) nrst schmitt trigger voltage hysteresis - 200 - mv r pu weak pull-up equivalent resistor (2) 2. the pull-up is designed with a true resistance in seri es with a switchable pmos . this pmos contribution to the series resistance must be minimum (~10% order) . v in = v ss 25 40 55 k v f(nrst) (1) nrst input filtered pulse - - 100 ns v nf(nrst) (1) nrst input not filtered pulse 300 - - ns - 3 6 2 0 5 . 2 3 4 6 $ $ & i l t e r ) n t e r n a l 2 e s e t ? & % x t e r n a l r e s e t c i r c u i t electrical characteristics stm32f050xx 72/97 doc id 023683 rev 1 6.3.15 12-bit adc characteristics unless otherwise specified, the parameters given in ta bl e 4 9 are preliminary values derived from tests performed under ambient temperature, f pclk2 frequency and v dda supply voltage conditions summarized in table 15: general operating conditions . note: it is recommended to perform a calibration after each power-up. table 49. adc characteristics symbol parameter conditions min typ max unit v dda analog supply voltage for adc on 2.4 - 3.6 v f adc adc clock frequency 0.6 - 14 mhz f s (1) sampling rate 0.05 - 1 mhz f trig (1) external trigger frequency f adc = 14 mhz - - 823 khz --171/f adc v ain conversion voltage range 0 - v dda v r ain (1) external input impedance see equation 1 and ta bl e 5 0 for details --50k r adc (1) sampling switch resistance - - 1 k c adc (1) internal sample and hold capacitor --8pf t cal (1) calibration time f adc = 14 mhz 5.9 s 83 1/f adc t latr (1) trigger conversion latency f adc = f pclk /2 = 14 mhz 0.196 s f adc = f pclk /2 5.5 1/f pclk f adc = f pclk /4 = 12 mhz 0.219 s f adc = f pclk /4 10.5 1/f pclk f adc = f hsi14 = 14 mhz 0.188 - 0.259 s jitter adc adc jitter on trigger conversion f adc = f hsi14 -1-1/f hsi14 t s (1) sampling time f adc = 14 mhz 0.107 - 17.1 s 1.5 - 239.5 1/f adc t stab (1) power-up time 0 0 1 s t conv (1) total conversion time (including sampling time) f adc = 14 mhz 1 18 s 14 to 252 (t s for sampling +12.5 for successive approximation) 1/f adc 1. guaranteed by design, not tested in production. stm32f050xx electrical characteristics doc id 023683 rev 1 73/97 equation 1: r ain max formula the formula above ( equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of lsb. here n = 12 (from 12-bit resolution). table 50. r ain max for f adc = 14 mhz (1) 1. guaranteed by design, not tested in production. t s (cycles) t s (s) r ain max (k ) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 na 239.5 17.1 na table 51. adc accuracy (1)(2) (3) 1. adc dc accuracy values are m easured after internal calibration. symbol parameter test conditions typ max (4) unit et total unadjusted error f pclk = 48 mhz, f adc = 14 mhz, r ain < 10 k , v dda = 3 v to 3.6 v t a = 25 c 1.3 2 lsb eo offset error 1 1.5 eg gain error 0.5 1.5 ed differential linearity error 0.7 1 el integral linearity error 0.8 1.5 et total unadjusted error f pclk = 48 mhz, f adc = 14 mhz, r ain < 10 k , v dda = 2.7 v to 3.6 v t a = ? 40 to 105 c 3.3 4 lsb eo offset error 1.9 2.8 eg gain error 2.8 3 ed differential linearity error 0.7 1.3 el integral linearity error 1.2 1.7 et total unadjusted error f pclk = 48 mhz, f adc = 14 mhz, r ain < 10 k , v dda = 2.4 v to 3.6 v t a = 25 c 3.3 4 lsb eo offset error 1.9 2.8 eg gain error 2.8 3 ed differential linearity error 0.7 1.3 el integral linearity error 1.2 1.7 r ain t s f adc c adc 2 n2 + () ln --------------------------------------------------------------- - r adc ? < electrical characteristics stm32f050xx 74/97 doc id 023683 rev 1 figure 24. adc accuracy characteristics figure 25. typical connection diagram using the adc 1. refer to table 49: adc characteristics for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. general pcb design guidelines power supply decoupling should be performed as shown in figure 10 . the 10 nf capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. 2. adc accuracy vs. negative injection current: in jecting negative current on any of the standard (non- robust) analog input pins should be av oided as this significantly reduce s the accuracy of the conversion being performed on another analog input. it is recommend ed to add a schottky diode (pin to ground) to standard analog pins which may pot entially inject negative current. any positive injection current with in the limits specified for i inj(pin) and i inj(pin) in section 6.3.13 does not affect the adc accuracy. 3. better performance may be achieved in restricted v dda , frequency and temperature ranges. 4. data based on characterization results, not tested in production. e o e g 1lsb ideal (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. 4095 4094 4093 5 4 3 2 1 0 7 6 1234567 4093 4094 4095 4096 (1) (2) e t e d e l (3) v dda v ssa - 3 6 1lsb ideal v dda - 3 6 6 $ $ ! ainx i l 1 a 0.6 v v t r ain (1) c parasitic v ain 0.6 v v t r adc 12-bit converter c adc sample and hold adc converter stm32f050xx electrical characteristics doc id 023683 rev 1 75/97 6.3.16 temperature sen sor characteristics 6.3.17 v bat monitoring characteristics 6.3.18 timer characteristics the parameters given in ta bl e 5 4 are guaranteed by design. refer to section 6.3.13: i/o port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output). table 52. ts characteristics symbol parameter min typ max unit t l (1) 1. guaranteed by design, not tested in production. v sense linearity with temperature - 1 2c avg_slope (1) average slope 4.0 4.3 4.6 mv/c v 25 voltage at 25 c 1.34 1.43 1.52 v t start (1) startup time 4 - 10 s t s_temp (1)(2) 2. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the temperature 17.1 - - s table 53. v bat monitoring characteristics symbol parameter min typ max unit r resistor bridge for v bat -50-k q ratio on v bat measurement - 2 - er (1) 1. guaranteed by design, not tested in production. error on q ?1 - +1 % t s_vbat (1)(2) 2. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the v bat 1mv accuracy 5- -s table 54. timx (1) characteristics symbol parameter conditions min max unit t res(tim) timer resolution time 1- t timxclk f timxclk = 48 mhz 20.8 - ns f ext timer external clock frequency on ch1 to ch4 0 f timxclk /2 mhz f timxclk = 48 mhz 0 24 mhz res tim timer resolution timx (except tim2) - 16 bit tim2 - 32 electrical characteristics stm32f050xx 76/97 doc id 023683 rev 1 t counter 16-bit counter clock period 1 65536 t timxclk f timxclk = 48 mhz 0.0208 1365 s t max_count maximum possible count with 32-bit counter - 65536 65536 t timxclk f timxclk = 48 mhz - 89.48 s 1. timx is used as a general term to refer to the tim1, tim2, tim3, tim6, tim14, tim15, tim16 and tim17 timers. table 55. iwdg min/max timeout period at 40 khz (lsi) (1) 1. these timings are given for a 40 khz clock but the microcontroller?s internal rc frequency can vary from 30 to 60 khz. moreover, given an exact rc oscillator frequency, t he exact timings still depend on the phasing of the apb interface clock versus the lsi clock so that there is always a full rc period of uncertainty. prescaler divider pr[2:0] bits min timeout rl[11:0]= 0x000 max timeout rl[11:0]= 0xfff unit /4 0 0.1 409.6 ms /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 6 or 7 6.4 26214.4 table 56. wwdg min-max timeout value @48 mhz (pclk) prescaler wdgtb min timeout value max timeout value unit 1 0 0.0853 5.4613 ms 2 1 0.1706 10.9226 4 2 0.3413 21.8453 8 3 0.6826 43.6906 table 54. timx (1) characteristics (continued) symbol parameter conditions min max unit stm32f050xx electrical characteristics doc id 023683 rev 1 77/97 6.3.19 communication interfaces i 2 c interface characteristics unless otherwise specified, the parameters given in ta bl e 5 7 are derived from tests performed under ambient temperature, f pclk frequency and v dd supply voltage conditions summarized in table 15: general operating conditions . the i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following restrictions: the i/o pins sda and scl are mapped to are not ?true? open- drain. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. the i 2 c characteristics are described in ta b l e 5 7 . refer also to section 6.3.13: i/o port characteristics for more details on the input/output alternate function characteristics (sda and scl) . table 57. i 2 c characteristics (1) symbol parameter standard mode fast mode fast mode plus unit min max min max min max t w(scll) scl clock low time 4.7 - 1.3 - 0.5 - s t w(sclh) scl clock high time 4.0 - 0.6 - 0.26 - t su(sda) sda setup time 250 - 100 - 50 - ns t h(sda) sda data hold time 0 (3) 3450 (2) 0 (3) 900 (2) 0 (4) 450 (2) t r(sda) t r(scl) sda and scl rise time - 1000 - 300 - 120 t f(sda) t f(scl) sda and scl fall time - 300 - 300 - 120 t h(sta) start condition hold time 4.0 - 0.6 - 0.26 - s t su(sta) repeated start condition setup time 4.7 - 0.6 - 0.26 - t su(sto) stop condition setup time 4.0 - 0.6 - 0.26 - s t w(sto:sta) stop to start condition time (bus free) 4.7 - 1.3 - 0.5 - s c b capacitive load for each bus line - 400 - 400 - 550 pf 1. the i2c characteristics are the requirements from i2c bus specification rev03. they are guaranteed by design when i2cx_timing register is correctly progr ammed (refer to reference manual). th ese characteristics are not tested in production. 2. the maximum data hold time has only to be met if the interface does not stretch the low period of scl signal. 3. the device must internally provide a hol d time of at least 300ns for the sda si gnal in order to bridge the undefined region of the falling edge of scl. 4. the device must internally provide a hol d time of at least 120ns for the sda si gnal in order to bridge the undefined region of the falling edge of scl. electrical characteristics stm32f050xx 78/97 doc id 023683 rev 1 figure 26. i 2 c bus ac waveforms and measurement circuit 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . spi/i 2 s characteristics unless otherwise specified, the parameters given in ta bl e 5 9 for spi or in ta bl e 6 0 for i 2 s are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 15: general operating conditions . refer to section 6.3.13: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso for spi and ws, ck, sd for i 2 s). table 58. i2c analog filter characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter min max unit t sp pulse width of spikes that are suppressed by the analog filter 50 260 ns - 3 6 3 4 ! 2 4 3 $ ! ) # b u s 2 6 $ $ 6 $ $ - # 5 3 $ ! 3 # , t f 3 $ ! t r 3 $ ! 3 # , t h 3 4 ! t w 3 # , ( t w 3 # , , t s u 3 $ ! t r 3 # , t f 3 # , t h 3 $ ! 3 4 ! 2 4 2 % 0 % ! 4 % $ 3 4 ! 2 4 t s u 3 4 ! t s u 3 4 / 3 4 / 0 t w 3 4 / 3 4 ! 2 stm32f050xx electrical characteristics doc id 023683 rev 1 79/97 table 59. spi characteristics symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master mode - 18 mhz slave mode - 18 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 15 pf - 6 ns t su(nss) (1) nss setup time slave mode 4tpclk - ns t h(nss) (1) nss hold time slave mode 2tpclk + 10 - t w(sckh) (1) t w(sckl) (1) sck high and low time master mode, f pclk = 36 mhz, presc = 4 tpclk/2 -2 tpclk/2 + 1 t su(mi) (1) t su(si) (1) data input setup time master mode 4 - slave mode 5 - t h(mi) (1) data input hold time master mode 4 - t h(si) (1) slave mode 5 - t a(so) (1)(2) data output access time slave mode, f pclk = 20 mhz 0 3tpclk t dis(so) (1)(3) data output disable time slave mode 0 18 t v(so) (1) data output valid time slave mode (after enable edge) - 22.5 t v(mo) (1) data output valid time master mode (after enable edge) - 6 t h(so) (1) data output hold time slave mode (after enable edge) 11.5 - t h(mo) (1) master mode (after enable edge) 2 - ducy(sck) spi slave input clock duty cycle slave mode 25 75 % 1. data based on characterization results, not tested in production. 2. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z electrical characteristics stm32f050xx 80/97 doc id 023683 rev 1 figure 27. spi timing diagram - slave mode and cpha = 0 figure 28. spi timing diagram - slave mode and cpha = 1 (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14134c sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input stm32f050xx electrical characteristics doc id 023683 rev 1 81/97 figure 29. spi timing diagram - master mode (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14136 sck output cpha= 0 mosi outut miso inp ut cpha= 0 ms bin m sb out bi t6 in lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck output cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo) electrical characteristics stm32f050xx 82/97 doc id 023683 rev 1 table 60. i 2 s characteristics symbol parameter conditions min max unit f ck 1/t c(ck) i 2 s clock frequency master mode (data: 16 bits, audio frequency = 48 khz) 1.597 1.601 mhz slave mode 0 6.5 t r(ck) i 2 s clock rise time capacitive load c l =15pf -10 ns t f(ck) i 2 s clock fall time - 12 t w(ckh) (1) i2s clock high time master f pclk = 16 mhz, audio frequency = 48 khz 306 - t w(ckl) (1) i2s clock low time 312 - t v(ws) (1) ws valid time master mode 2 - t h(ws) (1) ws hold time master mode 2 - t su(ws) (1) ws setup time slave mode 7 - t h(ws) (1) ws hold time slave mode 0 - ducy(sck) i2s slave input clock duty cycle slave mode 25 75 % t su(sd_mr) (1) data input setup time master receiver 6 - ns t su(sd_sr) (1) data input setup time slave receiver 2 - t h(sd_mr) (1)(2) data input hold time master receiver 4 - t h(sd_sr) (1)(2) slave receiver 0.5 - t v(sd_st) (1)(2) data output valid time slave transmitter (after enable edge) -20 t h(sd_st) (1) data output hold time slave transmitter (after enable edge) 13 - t v(sd_mt) (1)(2) data output valid time master transmitter (after enable edge) - 4 t h(sd_mt) (1) data output hold time master transmitter (after enable edge) 0- 1. data based on design simulation and/or char acterization results, not tested in production. 2. depends on f pclk . for example, if f pclk =8 mhz, then t pclk = 1/f plclk =125 ns. stm32f050xx electrical characteristics doc id 023683 rev 1 83/97 figure 30. i2s slave timing diagram (philips protocol) 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. figure 31. i2s master timing diagram (philips protocol) 1. data based on characterization results, not tested in production. 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. ck inp u t cpol = 0 cpol = 1 t c(ck) w s inp u t s d tr a n s mit s d receive t w(ckh) t w(ckl) t su (w s ) t v( s d_ s t) t h( s d_ s t) t h(w s ) t su ( s d_ s r) t h( s d_ s r) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14 88 1 b l s b receive (2) l s b tr a n s mit (2) ck o u tp u t cpol = 0 cpol = 1 t c(ck) w s o u tp u t s d receive s d tr a n s mit t w(ckh) t w(ckl) t su ( s d_mr) t v( s d_mt) t h( s d_mt) t h(w s ) t h( s d_mr) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14 88 4 b t f(ck) t r(ck) t v(w s ) l s b receive (2) l s b tr a n s mit (2) package characteristics stm32f050xx 84/97 doc id 023683 rev 1 7 package characteristics 7.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. stm32f050xx package characteristics doc id 023683 rev 1 85/97 figure 32. lqfp48 - 7 x 7 mm, 48-pin low-profile quad flat package outline 1. drawing is not to scale. 5b_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 24 25 36 37 b 48 1 pin 1 identification 12 13 table 61. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0. 0531 0.0551 0.0571 b 0.170 0.220 0.270 0. 0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 8.800 9.000 9.200 0. 3465 0.3543 0.3622 d1 6.800 7.000 7.200 0. 2677 0.2756 0.2835 d3 5.500 0.2165 e 8.800 9.000 9.200 0. 3465 0.3543 0.3622 e1 6.800 7.000 7.200 0. 2677 0.2756 0.2835 e3 5.500 0.2165 e 0.500 0.0197 l 0.450 0.600 0.750 0. 0177 0.0236 0.0295 l1 1.000 0.0394 k 03.57 03.57 ccc 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. package characteristics stm32f050xx 86/97 doc id 023683 rev 1 figure 33. lqfp48 recommended footprint 1. drawing is not to scale. 2. dimensions are in millimeters. 9.70 5.80 7.30 12 24 0.20 7.30 1 37 36 1.20 5.80 9.70 0.30 25 1.20 0.50 ai14911b 13 48 stm32f050xx package characteristics doc id 023683 rev 1 87/97 figure 34. ufqfpn32 - 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package outline 1. drawing is not to scale. 2. all leads/pads should also be soldered to the pcb to improve the lead/pad solder joint life. 3. there is an exposed die pad on the underside of the ufqf pn package. this pad is used for the device ground and must be connected. it is referred to as pin 0 in table 8: pin definitions . s e a ting pl a ne ddd c c a 3 a1 a d e 9 16 17 24 3 2 pin # 1 id r = 0. 3 0 8 e l l d2 1 b e2 a0b 8 _me bottom view table 62. ufqfpn32 ? 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package mechanical data dim. millimeters inches (1) min typ max min typ max a 0.5 0.55 0.6 0.0197 0.0217 0.0236 a1 0.00 0.02 0.05 0 0.0008 0.0020 a3 0.152 0.006 b 0.18 0.23 0.28 0.0071 0.0091 0.0110 d 4.90 5.00 5.10 0.1929 0.1969 0.2008 d2 3.50 0.1378 e 4.90 5.00 5.10 0.1929 0.1969 0.2008 e2 3.40 3.50 3.60 0.1339 0.1378 0.1417 e 0.500 0.0197 l 0.30 0.40 0.50 0.0118 0.0157 0.0197 ddd 0.08 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. package characteristics stm32f050xx 88/97 doc id 023683 rev 1 figure 35. ufqfpn32 recommended footprint 1. drawing is not to scale. 2. dimensions are in millimeters. stm32f050xx package characteristics doc id 023683 rev 1 89/97 figure 36. ufqfpn28 - 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package outline 1. drawing is not to scale. 2. dimensions are in millimeters. 3. all leads/pads should also be soldered to the pcb to improve the lead/pad solder joint life. x 4 e b 3 e a t i n g 0 l a n e ! ! # o x ? 0 i n c o r n e r , , 2 o 4 y p $ e t a i l : $ $ % % 0 i n ) $ 3 e a t i n g 0 l a n e " ! $ e t a i l : ! " ? - % ? 6 table 63. ufqfpn28 ? 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package mechanical data symbol millimeters inches (1) min typ max min typ max a 0.5 0.55 0.6 0.0197 0.0217 0.0236 a1 -0.05 0 0.05 -0.002 0 0.002 d 3.9 4 4.1 0.1535 0.1575 0.1614 d1 2.9 3 3.1 0.1142 0.1181 0.122 e 3.9 4 4.1 0.1535 0.1575 0.1614 e1 2.9 3 3.1 0.1142 0.1181 0.122 l 0.3 0.4 0.5 0.0118 0.0157 0.0197 l1 0.25 0.35 0.45 0.0098 0.0138 0.0177 t 0.152 0.006 b 0.2 0.25 0.3 0.0079 0.0098 0.0118 e 0.5 0.0197 1. values in inches are converted from mm and rounded to 4 decimal digits. package characteristics stm32f050xx 90/97 doc id 023683 rev 1 figure 37. ufqfpn28 recommended footprint 1. dimensions are in millimeters 2. all leads/pads should also be soldered to the pcb to improve the lead/pad solder joint life. ! " ? - % ? & 0 stm32f050xx package characteristics doc id 023683 rev 1 91/97 figure 38. tssop20 - 20-pin thin shrink small outline 1. drawing is not to scale. 9 ! ? - % # 0 c , % % $ ! ! k e b ! , a a a table 64. tssop20 ? 20-pin thin shrink small outline package mechanical data symbol millimeters inches (1) min typ max min typ a 1.2 0.0472 a1 0.05 0.15 0.002 0.0059 a2 0.8 1 1.05 0.0315 0.0394 0.0413 b 0.19 0.3 0.0075 0.0118 c 0.09 0.2 0.0035 0.0079 d 6.4 6.5 6.6 0.252 0.2559 0.2598 e 6.2 6.4 6.6 0.2441 0.252 0.2598 e1 4.3 4.4 4.5 0.1693 0.1732 0.1772 e 0.65 0.0256 l 0.45 0.6 0.75 0.0177 0.0236 0.0295 l1 1 0.0394 k 0.0 8.0 0.0 8.0 aaa 0.1 0.0039 1. values in inches are converted from mm and rounded to 4 decimal digits. package characteristics stm32f050xx 92/97 doc id 023683 rev 1 figure 39. tssop20 recommended footprint 1. dimensions are in millimeters stm32f050xx package characteristics doc id 023683 rev 1 93/97 7.2 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in table 15: general operating conditions on page 39 . the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ja ) where: t a max is the maximum ambient temperature in c, ja is the package junction-to-ambient thermal resistance, in c/w, p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), p int max is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/o max represents the maximum powe r dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 7.2.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). ava ilable from www.jedec.org 7.2.2 selecting the pro duct temperature range when ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in section 8: part numbering . each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. as applications do not commonly use the stm32f05xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. the following examples show how to calculate the temperature range needed for a given application. table 65. package thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lqfp48 - 7 7 mm 55 c/w thermal resistance junction-ambient ufqfpn32 - 5 5 mm 38 thermal resistance junction-ambient ufqfpn28 - 4 4 mm 118 thermal resistance junction-ambient tssop20 110 package characteristics stm32f050xx 94/97 doc id 023683 rev 1 example 1: high-performance application assuming the following application conditions: maximum ambient temperature t amax = 80 c (measured according to jesd51-2), i ddmax = 50 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v and maximum 8 i/os used at the same time in output at low level with i ol = 20 ma, v ol = 1.3 v p intmax = 50 ma 3.5 v= 175 mw p iomax = 20 8 ma 0.4 v + 8 20 ma 1.3 v = 272 mw this gives: p intmax = 175 mw and p iomax = 272 mw: p dmax = 175 + 272 = 447 mw using the values obtained in ta b l e 6 5 t jmax is calculated as follows: ? for lqfp48, 55 c/w t jmax = 80 c + (55c/w 447 mw) = 80 c + 24.585 c = 104.585 c this is within the range of the suffix 6 version parts (?40 < t j < 105 c) see ta bl e 1 5 : general operating conditions on page 39 . in this case, parts must be ordered at least with the temperature range suffix 6 (see section 8: part numbering ). note: with this given p dmax we can find the t amax allowed for a given device temperature range (order code suffix 6 or 7). suffix 6: t amax = t jmax - (55c/w 447 mw) = 105-24.585 = 80.415 c suffix 7: t amax = t jmax - (55c/w 447 mw) = 125-24.585 = 100.415 c example 2: high-temperature application using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature t j remains within the specified range. assuming the following application conditions: maximum ambient temperature t amax = 100 c (measured according to jesd51-2), i ddmax = 20 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 20 ma 3.5 v= 70 mw p iomax = 20 8 ma 0.4 v = 64 mw this gives: p intmax = 70 mw and p iomax = 64 mw: p dmax = 70 + 64 = 134 mw thus: p dmax = 134 mw using the values obtained in ta b l e 6 5 t jmax is calculated as follows: ? for lqfp48, 55 c/w t jmax = 100 c + (55 c/w 134 mw) = 100 c + 7.37 c = 107.37 c this is above the range of the suffix 6 version parts (?40 < t j < 105 c). in this case, parts must be ordered at least with the temperature range suffix 7 (see section 8: part numbering ) unless we reduce the power dissipation in order to be able to use suffix 6 parts. stm32f050xx part numbering doc id 023683 rev 1 95/97 8 part numbering for a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest st sales office. example :stm32f050c6t6ax device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose sub-family 050 = stm32f050xx pin count f = 20 pins g = 28 pins k = 32 pins c = 48 pins code size 4 = 16 kbytes of flash memory 6 = 32 kbytes of flash memory package p = tssop u = ufqfpn t = lqfp temperature range 6 = ?40 c to +85 c 7 = ?40 c to +105 c internal code a = non-optimized die blank = standard die options xxx = programmed parts tr = tape and real revision history stm32f050xx 96/97 doc id 023683 rev 1 9 revision history table 66. document revision history date revision changes 22-nov-2012 1 initial release stm32f050xx doc id 023683 rev 1 97/97 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 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